Jing-Fu Jenq

Reconfigurable mesh algorithms for the Hough transform

Abstract We develop parallel algorithms to compute the Hough transform on a reconfigurable mesh with buses (RMESH) multiprocessor. The p angle Hough transform of an N × N image can be computed in O(p log(N/p)) time by an N × N RMESH, in O((p/N) log N) time by an N × N2 RMESH with N copies of the image pretiled, in O((p/[formula]) log N) time by an N1.5 × N1.5 RMESH, and in O((p/N) log N) time by an N2 × N2 RMESH.

Image shrinking and expanding on a pyramid

Develops two algorithms to perform the q step shrinking and expanding of an N*N binary image on a pyramid computer with an N*N base. The time complexity of both algorithms is O( square root q). However, one uses O( square root q) space per processor, while the per-processor space requirement of the other is O(1). >

Histogramming on a reconfigurable mesh computer

The authors develop reconfigurable mesh (RMESH) algorithms for window broadcasting, data shifts and consecutive sum. These are then used to develop efficient algorithms to compute the histogram of an image and to perform histogram modification. The histogram of an N*N image is computed by an N*N RMESH in O( square root B log /sub square root B/(N/ square root B) for B<N, O( square root N) for B=N, and O( square root B) for N<B<or=N/sup 2/. B is the number of gray scale values. Histogram modification is done in O( square root N) time by an N*N RMESH.<<ETX>>

Reconfigurable Mesh Algorithms For Fundamental Data Manipulation Operations

Reconfigurable mesh (RMESH) algorithms for several fundamental operations are developed. These operations include data broadcast, prefix sum, data sum, ranking, shift, data accumulation, consecutive sum, adjacent sum, sorting, random access read, and random access write.

Computing the configuration space for a convex robot on hypercube multiprocessors

Computing the configuration space obstacles is an important problem in spatial planning for robotics applications. In this paper we present a parallel algorithm for computing the configuration space obstacles by using hypercube multiprocessors. The digitized images of the obstacles and the robot are stored in an N/spl times/N image plane. An algorithm for handling robots whose shapes are arbitrary convex polygons was presented. Our algorithms take O(logN) time and O(I) space which is asymptotically optimal for hypercube computers.

Serial and parallel algorithms for the medial axis transform

The authors develop an O(n/sup 2/) time serial algorithm to obtain the medial axis transform (MAT) of an n*n image. An O(logn) time CREW PRAM algorithm and an O(log/sup 2/n) time SIMD hypercube parallel algorithm for the MAT are also developed. Both of these use O(n/sup 2/) processors. Two problems associated with the MAT are also studied. These are the area and perimeter reporting problem. The authors develop an O(logn) time hypercube algorithm for both of these problems. Here n is the number of squares in the MAT and the algorithms use O(n/sup 2/) processors.<<ETX>>

Artificial neural networks on reconfigurable meshes

Artificial neural networks(ANN) have been used successfully in applications such as pattern recognition, image processing, automation and control. Majority of todays applications use backpropagate feedforward ANN. In this paper, two methods of P pattern L layer ANN learning on n x n RMESH have been presented. One required memory space of O(nL) but conceptually is simpler to develop and the other uses pipelined approach which reduces the memory requirement to O(L). Both of these algorithms take O(PL) time and are optimal for RMESH architecture.

Image Processing On Reconfigurable Meshes With Buses

Abstract In this chapter, we describe different reconfigurable mesh with buses architectures and show how several image processing problems can be solved efficiently on the weakest of these. The specific problems considered are: area and perimeter of components, shrinking and expanding, clustering, and template matching. In many cases, the resulting algorithms are faster than those for other parallel computer architectures.