Jing Pu

Heterogeneous Si/III-V integration and the optical vertical interconnect access

A new heterogeneous Si/III-V integration and the optical vertical interconnect access to the silicon-on-insulator (SOI) nanophotonic layer is proposed and designed. The III-V semiconductor layers are directly bonded to the SOI layer and etched to form the Si/III-V waveguide (after removal of the substrate), which has no air-trench or SOI channel waveguide underneath as the prior art. The design example shows a 1.5 μm wide Si/III-V waveguide has a confinement factor of ~24% in a 100 nm-thick active region for effective light amplification/absorption. The optical vertical interconnect access is realized through tapering both the III-V semiconductor waveguide and SOI layer in the same direction. Optimization using a simple approximated two-dimensional modal presented gives ~100% coupling efficiency with a 25 μm long optical vertical interconnect access. A three-dimensional finite-difference-time-domain electromagnetic simulation verifies the design numerically and also shows the proposed structure has a good alignment tolerance for fabrication.

Demonstration of heterogeneous III–V/Si integration with a compact optical vertical interconnect access

Heterogeneous III-V/Si integration with a compact optical vertical interconnect access is fabricated and the light coupling efficiency between the III-V/Si waveguide and the silicon nanophotonic waveguide is characterized. The III-V semiconductor material is directly bonded to the silicon-on-insulator (SOI) substrate and etched to form the III-V/Si waveguide for a higher light confinement in the active region. The compact optical vertical interconnect access is formed through tapering a III-V and an SOI layer in the same direction. The measured III-V/Si waveguide has a light coupling efficiency above ~90% to the silicon photonic layer with the tapering structure. This heterogeneous and light coupling structure can provide an efficient platform for photonic systems on chip, including passive and active devices.

Generic Heterogeneously Integrated III–V Lasers-on-Chip With Metal-Coated Etched-Mirror

In this paper, electrically pumped III-V quantum-well lasers bonded on SiO2 with a metal-coated etched-mirror are reported. There are three key features for the device demonstrated: (i) The metal-coated etched-mirror ensures that the lasers can be used as on-chip light source and provides high reflectance, but requires no additional fabrication steps due to our process design, (ii) the bonded III-V on SiO2 enables high-light confinement in the active region due to high index contrast between III-V and SiO2. Moreover, it promises a flexible choice of host substrate, in which the silicon substrate could also be replaced with other materials, and (iii) the active III-V region is sufficiently close to the SiO2 interlayer, allowing the laser mode to overlap with SiO2. This facilitates effective optical coupling with in-plane passive waveguides, which can be fabricated from thin film of amorphous silicon, silicon nitride or other waveguide materials, to form a subsystem on chip through in-plane integration. The laser devices demonstrated have the lowest threshold of 50 mA, a maximum output power of 9 mW, and a differential quantum efficiency of 27.6%.

Heterogeneously integrated III-V laser on thin SOI with compact optical vertical interconnect access.

A new heterogeneously integrated III-V/Si laser structure is reported in this report that consists of a III-V ridge waveguide gain section on silicon, III-V/Si optical vertical interconnect accesses (VIAs), and silicon-on-insulator (SOI) nanophotonic waveguide sections. The III-V semiconductor layers are introduced on top of the 300-nm-thick SOI layer through low temperature, plasma-assisted direct wafer-bonding and etched to form a III-V ridge waveguide on silicon as the gain section. The optical VIA is formed by tapering the III-V and the beneath SOI in the same direction with a length of 50 μm for efficient coupling of light down to the 600 nm wide silicon nanophotonic waveguide or vice versa. Fabrication details and specification characterizations of this heterogeneous III-V/Si Fabry-Perot (FP) laser are given. The fabricated FP laser shows a continuous-wave lasing with a threshold current of 65 mA at room temperature, and the slope efficiency from single facet is 144  mW/A. The maximal single facet emitting power is about 4.5 mW at a current of 100 mA, and the side-mode suppression ratio is ∼30  dB. This new heterogeneously integrated III-V/Si laser structure demonstrated enables more complex laser configuration with a sub-system on-chip for various applications.

Heterogeneous Integrated III–V Laser on Thin SOI With Single-Stage Adiabatic Coupler: Device Realization and Performance Analysis

A III-V on silicon heterogeneous integrated laser with highly efficient single-stage adiabatic coupler is presented in this paper. The structure consists of an electrically pumped III-V ridge waveguide gain section on silicon, III-V/Si optical adiabatic coupler, and silicon-on-insulator (SOI) nanophotonic waveguide. The adiabatic coupler is 50-μm long and is formed by tapering the III-V ridge and the underneath thin SOI waveguide along the same direction for efficient coupling of light between III-V ridge and silicon waveguide. Fabrication details and characterizations of this heterogeneous III-V/Si Fabry-Pérot (FP) laser are presented. Experimental data show that such structure has a low taper end reflection of ~-37 dB, and a high optical coupling efficiency of ~85%. The fabricated FP laser shows a high differential quantum efficiency of 23.78% under pulse operation at room temperature. The maximal single facet emitting power is about 7.5 mW, and the side-mode suppression ratio is ~30 dB. Thermal characterization shows a length normalized thermal independence of 20.02 °C·mm/W. Since this new heterogeneously integrated III-V/Si laser structure is realized directly on thin SOI, it offers a potential solution for developing more complex, efficient, and scalable integrated on-chip subsystems for various applications.

Effects of SiO 2 hard masks on si nanophotonic waveguide loss for photonic device integration

As the basic building block for photonic device integration, silicon nanophotonic waveguide requires low-loss propagation for high-performance ultra-compact photonic device. We experimentally study silicon dioxide hard masks grown by two different methods, i.e., thermal oxidation and plasma-enhanced chemical vapor deposition (PECVD) for silicon nano-waveguides fabrication and their effects on the propagation loss. It is found that the denser and smoother quality of thermally grown silicon dioxide increases the etch selectivity against silicon and reduces the line edge roughness transferred to the silicon nano-waveguide sidewalls, hence resulting in a lower loss as compared with the PECVD silicon dioxide hard mask. With thermally grown silicon dioxide as a hard mask, the silicon nano-waveguides loss can be halved for a 650-nm-wide nano-waveguide, and the loss is comparable with a waveguide fabricated with a resist etch mask.

A Theoretical and Experimental Study of Silicon Y-Branch Micro-Loop Reflectors

Y-branch micro-loop reflectors based on silicon nano-waveguides are designed, fabricated, and tested for maximizing the reflectivity in this letter. Our theoretical analysis suggests that a maximum reflectivity and a suppressed wavelength-sensitivity can be achieved by optimizing the waveguide dimensions of the Y-branch, given the phase distortion of the Y-branch is eliminated. The micro-loop reflector is fabricated on a silicon-on-insulator wafer, and the experimental results agree with the numerical analysis. The highest reflectivity achieved is 99.1% in the design and 89% in the experiment. This optimized Y-branch micro-loop reflector acts as a high-reflectivity reflector for chip-scale laser systems and integrated optical sensors.

Design, fabrication and demonstration of heterogeneously III-V/Si laser with a compact optical vertical interconnect access

A new heterogeneously integrated III-V/Si laser structure is reported in this letter, which consists of a III-V ridge waveguide gain section on silicon, III-V/Si optical vertical interconnect accesses (VIAs) and silicon-oninsulator (SOI) nanophotonic waveguide sections. The III-V semiconductor layers are introduced on top of the 300 nm thick SOI layer through low temperature, plasma assisted direct wafer-bonding and etched to form III-V ridge waveguide on silicon as the gain section. The optical VIA is formed by tapering the III-V and the beneath SOI in the same direction with a length of 50 μm for efficient coupling of light down to the 600 nm wide silicon nanophotonic waveguide or vice versa. Fabrication details and specification characterizations of this heterogeneous III-V/Si Fabry–Pérot (FP) laser are given. The fabricated FP laser shows a continuous-wave lasing with a threshold current of 65 mA at room temperature and the slope efficiency from single facet is 144 mW/A. The maximal single facet emitting power is about 4.5 mW at a current of 100 mA and the side-mode suppression ratio is ~30 dB. This new heterogeneously integrated III-V/Si laser structure demonstrated enables more complex laser configuration with a sub-system on-chip for various applications.

A novel type of ultra-compact lateral-current-injection III/V photonic device integrated on SOI for electronic-photonic chip application

An on-chip light source plays a determinant role in the realization of integrated photonic chips for optical interconnects technology. Several integration schemes of III/V laser on SOI platform for on-chip laser application have been proposed and demonstrated. However, most of those integration approaches do not provide effective solutions for the following two problems: effective light confinement/amplification in the III/V active region; and efficient light transfer/coupling between silicon and III/V waveguide. In this paper, a novel approach to integrate an ultra-compact Lateral-Current-Injection (LCI) laser on silicon-on-insulator (SOI) platform by direct wafer bonding technique is proposed and designed. The proposed LCI device has an ultra-thin thickness of 270 nm which is ~10 times thinner than the vertical current injection laser bonded on silicon. It has a confinement factor in the active region larger than 40% for 1 μm wide III/V active waveguide, which is the highest among all the other integration schemes proposed so far. An optical vertical interconnect access to transfer light efficiently between III/V and silicon layer is designed. The design of the shortest “Optical Via” of 4 μm which gives ~100% coupling efficiency is presented.

Hybrid integrated single-wavelength laser with silicon micro-ring reflector

A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.