Jing Wan

A tunneling field effect transistor model combining interband tunneling with channel transport

We present a model for the tunneling field-effect transistor (TFET) comprising a series connection of a metal-oxide-semiconductor FET (MOSFET) with a gate-controllable tunneling diode. Through the introduction of MOSFET in the model, both operational regimes of TFET are handled correctly, with the tunneling diode dominating at low interband tunneling current and the MOSFET component dominating at high tunneling current. The comparison between our model, TCAD simulations and experimental data on TFETs with different gate oxide and channel thicknesses over the full range of gate and drain bias confirms the model’s reliability and accuracy. At low tunneling current, the model further simplifies to a compact analytical model. With minor modifications, our model can also be applied to multi-gate TFET architectures.

A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration

We demonstrate experimentally a capacitor-less one-transistor dynamic random access memory (DRAM) based on fully depleted silicon-on-insulator substrate. In our device, the charges are directly stored in front gate capacitor (CG) and read out through a fast feedback regeneration process. The simulated read/write times of our device reach below 1 ns, much faster than conventional 1T-1C DRAM. The read/write biasing voltages can be scaled down to 1.1 V, achieving long retention time (tre >; 5s).

SOI TFETs: Suppression of ambipolar leakage and low-frequency noise behavior

We report on the thin-body tunneling field-effect transistors (TFETs) built on SOI substrates with both SiO2 and HfO2 gate dielectrics. The source-drain leakage current is suppressed by the introduction of intrinsic regions adjacent to the drain side, reducing the electric field at the tunnel junction. We also investigate the temperature dependence of the TFET characteristics, as well as the low frequency noise (LFN) behavior. Unlike conventional MOSFETs, the TFET LFN behaves as 1/ƒ2 even for large gate areas, indicating less trapping due to its much smaller effective gate length.

Low-frequency noise behavior of tunneling field effect transistors

We report on the low-frequency noise (LFN) properties of tunneling field effect transistors (TFETs) fabricated on silicon-on-insulator substrate. Unlike conventional large FETs, where LFN obeys a 1/f frequency dependence, in large TFETs the LFN is dominated by random telegraph signal (RTS) noise characterized by 1/f2 slope. We explain this unique LFN behavior by the local junction control of the tunneling drain current, which involves few traps in a small area. The origin of RTS noise is corroborated by the gate length independence of the ID-VGS characteristics of TFETs. The relatively high amplitude of RTS noise in TFETs will have circuit design implications.

A Review of Sharp-Switching Devices for Ultra-Low Power Applications

The reduction of the supply voltage is standard MOSFETs is impeded by the subthreshold slope, which cannot be lowered below 60 mV/decade, even in ideal fully-depleted devices. We review selected CMOS-compatible devices capable of switching more abruptly than MOSFETs, and discuss their merits and limitations. Tunneling FETs (TFETs) are reverse-biased gated PIN diodes where the gate controls the electric field in the interband tunneling junction. Technological solutions for improved performance will be described, including alternative channel materials and geometries, as well as a proposed paradigm shift of increasing the current drive by internal amplification in the bipolar-enhanced TFET. Other emerging sharp-switching mechanisms are reviewed, including the abrupt change in the polarization of ferroelectric materials, mechanical contact in nano-electro-mechanical systems, energy filtering of injected carriers, etc. Recently proposed band modulation feedback transistors are conceptually different from MOSFETs or TFETs. They have similar gated-diode configuration, but are operated in forward-bias mode. Electrostatic barriers are formed (via gate biasing) to prevent electron/hole injection into the channel until the gate or drain bias reaches a turn-on value. Due to bandgap modulation along the channel, these devices can switch abruptly (<;1 mV/decade) to a high current.

Novel Bipolar-Enhanced Tunneling FET With Simulated High On-Current

We propose and simulate a new device combining a tunneling field-effect transistor (TFET) with a heterojunction bipolar transistor (HBT). The carriers generated in the tunneling junction are used as base current to drive the HBT and obtain a high bipolar current. Owing to the sharp switching of the TFET and high HBT current gain, the CMOS-compatible Si/Si1-xGex device shows a subthreshold swing of <; 60 mV/ dec over seven decades of current, a high ON current, and scaling capability down to 10 nm.

Z 2 -FET: A zero-slope switching device with gate-controlled hysteresis

We present a novel switching device named Z²-FET that features zero subthreshold swing and zero impact ionization. The device is built in fully-depleted silicon-on-insulator (FD-SOI) technology and is demonstrated to switch sharply with the subthreshold slope (SS) <; 1 mV/dec and an I_ON/I_OFF current ratio >; 10¹⁰. The device further shows large hysteresis in drain current-drain voltage (I_D-V_D) domain with the turn-on voltage (V_ON) linearly controlled by gate voltage (V_G). Simulation confirms that the operation of the device is determined by the positive feedback between the flow of carriers and their injection barriers.

Z 2 -FET used as 1-transistor high-speed DRAM

We have recently demonstrated a new device named Z²-FET (zero subthreshold swing and zero impact ionization) and proposed it as a 1-transistor DRAM. The device is built on an FD-SOI substrate and operates by feedback between carrier flows and injection barriers. We now present additional results obtained from extensive experiments and simulations. Experimentally, the I_ON/I_OFF ratio exceeds 10⁹ and supply voltage (V_DD) scales down to 1.1 V with the DRAM retention time as high as 0.15 s at 75°C. In simulation, the access time reaches below 1 ns and the Z²-FET can be scaled down to 30 nm. We also discuss various operation modes.

Duplication of nanoimprint templates by a novel SU-8/SiO2/PMMA trilayer technique

In this work, a trilayer technique used in the nanoimprint lithography process to replicate the templates is developed. The SU8/SiO2/PMMA trilayer was used. The photosensitive epoxy (SU8 resist) which has a low glass transition temperature was used as the imprint layer. Polymethylmethacrylate (PMMA) was used as the transfer layer. A SiO2 layer is placed between the SU8 and PMMA to act as a protective layer due to its strong resistance to oxygen reactive ion etching. By optimizing imprint and etching processes, master templates with minimum feature size of 150 nm and period of 300 nm can be successfully duplicated.

APPLICATIONS OF NANOIMPRINT LITHOGRAPHY FOR BIOCHEMICAL AND NANOPHOTONIC STRUCTURES USING SU-8

Nanoimprint lithography (NIL) technology has aroused great interests in both academia and industry due to its high resolution, low-cost, and high-volume nanopatterning capability. And as an expoxy resin-based negative amplified photoresist, SU-8 is an ideal candidate for NIL because of its low-glass-transition temperature, low-volume shrinkage coefficient, and good optical properties. In this reviewing paper, we highlight the major technical achievements in NIL on epoxy resin and its applications for bio- and nanophotonic structures. NIL was also applied for the duplication of imprint templates, originally fabricated by e-beam lithography (EBL) followed by reactive ion etch (RIE), using a SU-8/SiO2/PMMA tri-layer technique. And nanoimprint properties were systematically investigated for optimization. The developed nanoimprint process for different applications indicates promising industrial potentials in the next generation lithography resolution.