Jing Wei-ping

Influence of Different Surface Modifications on the Photovoltaic Performance and Dark Current of Dye-Sensitized Solar Cells

The TiO2 nanoporous film photoelectrode, as a crucial component of dye-sensitized solar cells, has been investigated. The photovoltaic properties and the dark current were studied by two surface modification methods. One was to apply a compact layer between the conductive glass substrate and nanoporous TiO2 film. Another was to produce TiO2 nanoparticles among the microstructure by TiCl4 treatment. A suitable concentration and number of times for TiCl4 treatment were found in our experiment. The dark current is suppressed by surface modifications, leading to a significant improvement in the solar cells performance. An excessive concentration of TiCl4 will produce more surface states and introduce a larger dark current reversely. The dye is also regarded as a source of charge recombination in dark to some extent, due to an amount of surface protonations introduced by the interfacial link in the conductive glass substrate/dye interface and dye/TiO2 interface.

A Study on Porosity Distribution in Nanoporous TiO2 Photoelectrodes for Output Performance of Dye-Sensitized Solar Cells

Porosity as one of the crucial factors to film morphology affects the overall electrical current-voltage characteristics of dye-sensitized solar cell (DSC). We search for the short-circuit current density, the open-circuit voltage and the maximum power output as the main functional parameters of DSC closely related to porosity under different film thickness. The theoretical analyses show some exciting results. As porosity changes from 0.41 to 0.75, the short-circuit current density shows the optimal value when the film thickness is 8–10 μm. The open-circuit voltage presents different variation tendencies for the film thicknesses within 1–8 μm and within 10–30 μm. The porosity is near 0.41 and the film thickness is about 10 μm, DSC will have the maximum power output. The theoretical studies also illustrate that given a good porosity distribution, DSC can obtain an excellent short-circuit current characteristic, which agrees well with the experimental results reported in previous literature.

Signal-power integrity co-simulations of high speed systems via chip-package-PCB co-analysis methodology

Under the platform of a high-speed package system, a modeling method considering all the significant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity(SI/PI). For SI issues, accurate modelings for signal channel are verified by system of high speed line. The following what-if analyses help to identify the package traces bottlenecks and have great effects on signal transmission. For PI part, the modeling methodologies for power distribution networks of data line are demonstrated and validated with the results of frequency domain simulation. Lastly, with the co-simulations by chip-package-PCB model, the paper was talked about the SI and PI problem using SI-PI co-analysis methodology. The analysis results indicates that the parasitic effects of the high speed package system are the most critical, depicting the importance of improved package design in the next high speed package system.

A study on MAC sublayer of OBU in ETC system

In order to achieve the core chip which has the advantages of low cost, low power consumption and high integration in electronic toll collection system, the implementation of medium access control (MAC) sublayer protocol of the dedicated short-range communication is studied. Based on the analysis of working principle of MAC sublayer, the MAC sublayer is divided into three modules. Finally, the working process of every modules are realized in Verilog HDL, and the simulation results show that they are in accordance with the protocol.