Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Jing-Yuan Lin is active.

Publication


Featured researches published by Jing-Yuan Lin.


international microsystems, packaging, assembly and circuits technology conference | 2009

Novel Cu plating formula for filling through silicon vias

Shao-Ping Shen; Wei-Ping Dow; Motonobu Kubo; Tohru Kamitamari; Eric Cheng; Jing-Yuan Lin; Fu-Chiang Hsu

Through-silicon-via (TSV) technology has been employed for three-dimensional (3D) packaging of multi-chips. A high interwafer interconnect density can be achieved with a minor area penalty. Having shorter signal paths between dies make it possible to improve the systems performance by permitting the system to run faster, alleviate interconnect delay problems, it also consumes less power. Copper has been selected as the through-chop material because of its compatibility with conventional multilayer


international microsystems, packaging, assembly and circuits technology conference | 2011

A high temperature MEMS heater for optical sensors

Jing-Yuan Lin; Yu-Sheng Hsieh; Shang-Chian Su

Infrared light source is a key component in the optical sensing systems especially for the Fourier-Transformed Infrared (FTIR) or different kinds of gas sensor system. This paper proposes a novel method for generating a broadband wavelength infrared light source by MEMS heater based on silicon on insulator (SOI) technology. The enhanced long-tern stability has been achieved by a low electrical resistance SOI wafer. This novel MEMS heater can achieve over than 1000 °C. This MEMS heater could be integrated in micro sensing system such as metal oxide semiconductor and Non-dispersive infrared (NDIR) gas sensors.


international microsystems, packaging, assembly and circuits technology conference | 2010

A novel copper plating formula for through silicon holes filling in a center-up mode

Chun-Wei Lu; Jhih-Jyun Yan; Wei-Ping Dow; Jing-Yuan Lin

In recent years, through wafer electrical connections have become important roles, which will be used in developing high-speed, compact 3D microelectronic devices in next generation. Although the electroplating copper is a well-established process, completely void-free electroplating in through silicon holes (TSH) with a high aspect ratio remains a big challenge. Naturally, local current distribution is not uniform from the hole opening to the hole center during traditional electroplating. Therefore, voids were easily formed in TSH after traditional electroplating. In this paper, using this center-up technique, we demonstrate successful filling of though holes with an aspect ratio of 7.6. A novel copper plating formula composed of a special inhibitor achieved void-free copper could fill in TSH. Due to this special adsorption and inhibition of the new additive (VF-S), that have resulted in a concentration gradient of VF-S from the hole opening to the center, the center-up filling mode was carried out, meaning that copper pillars can be directly formed by copper electroplating without the need of a conducting template assembly.


Electrochemical and Solid State Letters | 2011

Highly Selective Cu Electrodeposition for Filling Through Silicon Holes

Wei-Ping Dow; Chun-Wei Lu; Jing-Yuan Lin; Fu-Chiang Hsu


Microelectronic Engineering | 2013

Copper seed layer repair using an electroplating process for through silicon via metallization

Shao-Ping Shen; Wei-Hsiang Chen; Wei-Ping Dow; Tohru Kamitamari; Eric Cheng; Jing-Yuan Lin; Wu-Chung Chang


ECS Electrochemistry Letters | 2013

Periodic Pulse Reverse Cu Plating for Through-Hole Filling

Fang-Yu Shen; Wei-Ping Dow; An-Hong Liu; Jing-Yuan Lin; Ping-He Chang; Su-Mei Huang


ECS Electrochemistry Letters | 2015

Microvia Filling with Nickel-Tungsten Alloy to Decrease the Coefficient of Thermal Expansion of Electronic Circuit Interconnections

Yu-Tien Lin; Hsin-Man Huang; Hsin-Wei Wang; Wei-Ping Dow; Jing-Yuan Lin; Ping-He Chang; Horn-Chin Lee


PRiME 2016/230th ECS Meeting (October 2-7, 2016) | 2016

Using Graphene As a Conducting and Barrier Layer for Filling through Silicon Vias with Co-W Alloy

Yi-Yong Chen; Wei-Ping Dow; Ping-He Chang; Hong-Qing Li; Jing-Yuan Lin


Meeting Abstracts | 2012

Periodic Pulse Reverse Cu Electroplating for Through Hole Filling

Fang-Yu Shen; Wei-Ping Dow; Jing-Yuan Lin; Wu-Chung Chang; Horn-Chin Lee


Meeting Abstracts | 2012

Cu Electroplating for Through Silicon Vias (TSVs) Filling Using a Dimensionally Stable Anode (DSA)

Wan Yun Hsiung; Wei-Ping Dow; Jing-Yuan Lin; Wu-Chung Chang; Horn-Chin Lee; Shih-Min Lin

Collaboration


Dive into the Jing-Yuan Lin's collaboration.

Top Co-Authors

Avatar

Wei-Ping Dow

National Chung Hsing University

View shared research outputs
Top Co-Authors

Avatar

Horn-Chin Lee

Industrial Technology Research Institute

View shared research outputs
Top Co-Authors

Avatar

Wu-Chung Chang

Industrial Technology Research Institute

View shared research outputs
Top Co-Authors

Avatar

Chun-Wei Lu

National Chung Hsing University

View shared research outputs
Top Co-Authors

Avatar

Fu-Chiang Hsu

Industrial Technology Research Institute

View shared research outputs
Top Co-Authors

Avatar

Shao-Ping Shen

National Chung Hsing University

View shared research outputs
Top Co-Authors

Avatar

Ping-He Chang

Industrial Technology Research Institute

View shared research outputs
Top Co-Authors

Avatar

Wei-Hsiang Chen

National Chung Hsing University

View shared research outputs
Top Co-Authors

Avatar

Fang-Yu Shen

National Chung Hsing University

View shared research outputs
Top Co-Authors

Avatar

Hsin-Man Huang

National Chung Hsing University

View shared research outputs
Researchain Logo
Decentralizing Knowledge