Jingning Liu

A Parity Scheme to Enhance Reliability for SSDs

Recent years, the application of solid-state disks (SSDs) increases explosively. All SSDs have to employ error correcting code (ECC) technique to ensure the reliability of flash memory at page level. However, data loss may be caused by bad block or chip failure of flash memory. To solve this problem, the article proposes a flash memory redundant array technique, which is similar to RAID-4. In this scheme, we utilize built-in NVRAM to cache the parity data update for minimal write to flash memory in parity channel.

DT-GC: Adaptive Garbage Collection with Dynamic Thresholds for SSDs

Solid state drives (SSDs) are rapidly growing used in both personal computer and enterprise server area in the past several years. Compare with traditional hard disk drive, the advantages of SSDs are great performance, small size and shock resistance. However, SSDs suffer from obvious performance dropping when free physical pages become lacking, after plenty of data writing. Because time-consuming garbage collection has to be ran to gaining enough free pages. Most algorithms determine a certain threshold of free page proportion, which could not adapt to various application environments, to trigger the garbage collection process. To achieve efficient garbage collection in most application environments, we propose DT-GC, an adaptive garbage collection method with dynamic thresholds. In such scheme, garbage collection request with different priority could be triggered intelligently by dynamic thresholds, which are determined by the running state of SSDs.

Implementation of FC-1 and FC-2 Layer for Multi-Gigabit Fibre Channel Transport

Fibre Channel (FC) is a high performance, low-latency data transfer technology that dominates todays high-end Storage Area Networks (SAN) market. This paper presents the design and implementation of Fibre Channel FC-1 and part of FC-2 layer for multi- gigabit Fibre Channel applications such as point-to-point and fabric interconnect. For efficient implementation, we have used the protocol-optimized hardware modules, such as on-the-fly CRC checking, frame length verification modules for frame receiving, CRC calculation and EOF generation modules for frame transmitting, to reduce the network latency. We also present an efficient method for buffer-to-buffer credit recovery, the basic idea of our method is to recover lost credits within the local as well as the remote port and avoid blocking of transmitters in long term. In the experiment, we build a 2G FC SCSI initiator using this logic core. The experimental results show that the initiator can reach a maximum throughput of 189.52MB/s for reading a RAMDisk target on the remote computer equipped with a QLA2310FCHBA.

A Write-Through Cache Method to Improve Small Write Performance of SSD-Based RAID

With the development of technology and price decline, flash-based Solid state drives (SSDs) are rapidly used to construct RAIDs by storage vendors. SSD does not need to seek and rotate, therefore, its read performance is much better than that of HDD. However, the small write performance of SSD is limited by its inherent characteristics such as out- of-place updates and garbage collection. The traditional parity-based RAID also has small write problem because of parity updating. SSD-based RAID, which is called RAIS, is generally based on the traditional RAID design and implementation. Consequently, handling small write requests is a serious challenge when SSD is used to construct parity-based RAID. In RAIS storage system, small write requests not only result in poor performance, but also shorten the lifetime of each SSD. In this paper, we propose a novel write through cache method, called CRAIS5, which uses a RAM as the write cache of RAIS5, and adopts the write-through mode to delay the parity update. The write-through cache method makes full use of the flash characteristics, and removes the pre-read operation. CRAIS5 improves the small write performance and reduces the erase time. We have implemented the CRAIS5 prototype in Disksim simulator, and used the real traces to evaluate the performance. The evaluations demonstrate that our CRAIS5 outperforms RAIS5, and PPC, on average, by 42.82%, and 34.49% respectively.

A Stripe-Oriented Write Performance Optimization for RAID-Structured Storage Systems

In modern RAID-structured storage systems, reliability is guaranteed by the use of parity blocks. But the parity-update overheads upon each write request have become a performance bottleneck of RAID systems. In some ways, an attached log disk is used to improve the write performance by delaying the parity blocks update. However, these methods are data-block-oriented and they need more time to rebuild or synchronize the RAID system when a data disk or the log disk fails. In this paper, we propose a novel optimization method, called SWO, which can improve RAID write performance and reconstruction performance. Moreover, when handling a write request, the SWO chooses reconstruction- write or read-modify-write combining with the log information to further minimize the number of pre- read data blocks. We have implemented the proposed SWO prototype and carried out some performance measurements using IOmeter and RAIDmeter. We have implemented the main idea of RAID6L in RAID5 and call it RAID5L. At the same time, we have evaluated the reconstruction time and the synchronization time of the SWO. Our experiments demonstrate that the SWO significantly improves write performance and saves more time than Data Logging and RAID5L when rebuilding and synchronizing.

Caching on dual-mode flash memory

NAND flash memory has attracted wide attention in both academia and industry in recent years. Its high random access performance fills the gap between DRAM and hard disks. While MLC is endorsed for higher density and lower cost per bit, it suffers from poor performance and endurance. Dual-mode flash combines SLC and MLC in a single device and thus provides the opportunity to trade density for performance. In this paper, we propose the Scalable Flash Storage(SFS) abstraction layer to facilitate cache management on dual-mode flash. SFS exposes a virtualized address space to hide the variable density of the medium. A differentiated write interface is introduced, which allows the cache manager to explicitly send write requests to SLC for high performance. SFS dynamically scales the proportions of SLC and MLC to balance between cache capacity and performance. SFS provides partially persistent storage service. It allows the cache manager to manage the data persistence on flash so that critical data can be retained persistently. Non-persistent data are discarded during garbage collection to mitigate write amplification. Based on the SFS, a Dual-mode Flash Cache(DMFC) architecture is designed to utilize the configurable density and performance. Experimental results show that DMFC can significantly improve overall performance for various workloads.

Parallel Aware Hybrid Solid-State Storage

Compared with tradition disk, NAND Flash has advantages of higher performance and shock resistance. But before write, NAND Flash must erase the old messages. That why NAND Flash based Solid State Disks (SSDs) always use the log-based schemes to improve the performance. Compared with NAND Flash, Phase Change Memory (PCM) has higher write performance, longer lifetime, and can update in-place, but its cost is high and capacity is low. So, in PCM and NAND Flash hybrid SSD, PCM is always used as log region, such as In-Page Logging-based (hybrid-IPL) SSD. The log-based SSD incurs a large number of merge operations. The cost of merge operation is very high because it involves many read, write operations, as well as an erase operation. So, how to reduce the cost of merge operations is the critical challenge to log-based hybrid (PCM and flash) SSD. In this paper, we propose a new merge scheme in PCM and NAND Flash hybrid SSD, called Parallel aware hybrid In-Page Logging-based (P-aware-IPL) SSD. This scheme can exploit the die-level and plane-level parallelism of flash. Leveraging these two levels of parallelism, the cost of full merge is significantly reduced compared with that of hybrid-IPL SSD scheme and there is no other additional overhead in our algorithm. Experiment results have shown that the proposed P-aware-IPL reduces the flash write and erase operations by up to 10 % and average response time by up to 22 % against the hybrid-IPL scheme.

Per-File Secure Deletion Combining with Enhanced Reliability for SSDs

Flash memory based Solid State Drives(SSDs) become an indispensable part in mobile computers. To protect confidential data from being leaked, user have to run secure deletion software to erase the confidential files. However the traditional secure deletion software may report success on SSDs, but do not work at all. To solve the problem, we proposed a per-file secure deletion method to clean up the sensitive data without erase the whole SSD. In addition, RAID technique is also employed to enhance the reliability and eliminate the potential risk caused by secure deletion.