Jinguang Jiang

0.5 V 1.3 GHz voltage controlled ring oscillator

A three stage ultra low power, low voltage ring oscillator is presented in this paper. The bulk of the PMOS transistor is used as the control voltage, the substrate of the NMOS transistor is also forward biased to reduce the threshold of the NMOS transistor for low voltage operation. The proposed VCO is designed and simulated in 0.18 µm RF CMOS process. Simulation results show that the proposed VCO can work at 0.5 V power supply, the oscillation frequency of VCO is from 124 MHz to 1.3 GHz. The power consumption is 85 µW when the VCO works at 1.3 GHz1.

A dual mode high efficiency buck DC-DC converter

This paper proposes a pulse width modulation-pulse skipping modulation (PWM-PSM) dual mode control and high efficiency buck dc-dc converter with 91.7% peak efficiency. A simple but steady PWM-PSM automatic switching module is proposed to improve the conversion efficiency when the load is light and synchronous rectifier is used to boost the conversion efficiency when the load is heavy. At the same time, a new saw tooth waveform generator is proposed to suit both the PWM and PSM. The dc-dc converter has been realized with a 0.18µm TSMC mixed-signal CMOS process and operates at 100 KHz with supply voltage from 4.5V to 5.5V which is the voltage range of USB interface. Measured conversion efficiency is over 80% for load current from 10mA to 600mA when the input voltage is 5V and output voltage is 3.3V.

A low phase noise and low spur PLL with auto frequency control circuit for L1-band GPS receiver

A low phase noise and low spur phase-locked loop (PLL) for L1-band global positioning system receiver is proposed in this paper. For obtaining low phase noise for PLL, All-PMOS LC-VCO with varactor-smoothing technique and noise-filtering technique is adopted. To reduce the reference spur, a low current-mismatch charge pump is carefully designed. A quasi-closed-loop auto frequency control circuit is used to accelerate the lock process of PLL. The PLL is fabricated in 180nm CMOS Mixed-Signal process while it operates under 1.8V supply voltage. The measured output frequency of PLL is 1.571GHz and output power is -1.418dBm. The in-band phase noise is -98.1 dBc/Hz @ 100kHz, while the out-band phase noise is -130.3dBc/Hz @ 1MHz. The reference spur is -75.8dBc at 16.368MHz offset. When quasi closed-loop AFC is working, the measured lock time is about 10.2µs.

Cascadable current-mode multifunction filter configuration using minimum number of CCTAs and grounded capacitors

A configuration is derived from signal flow graphs. A series of different order current-mode multifunction filters based on CCTAs can be obtained from the configuration. All the derived filters can simultaneously realize five primary responses from same topology. Both ω0 and Q can be tuned electronically independently over a wide range. Additionally, the configuration can be easily cascaded to obtain an nth-order filter which is only composed by n CCTAs and n grounded capacitors. The proposed configuration has simple structure, and is highly suitable for IC implementation. The realized circuits are simulated with SPICE to exhibit the performance.

Current-mode square-wave converter with current-rectifying function employing MOCCII

This paper proposed a novel tunable current-mode square-wave converter with current-rectifying function. The converter has a concise and simple structure without using any passive devices, and all the active devices of the converter are grounded, which makes it convenient for IC application. The proposed converter can generate both positive and negative square-wave signals whose amplitude can be adjusted independently by the bias ports. Also it can produce positive half-wave, negative half-wave, positive full-wave, and negative full-wave rectifying current outputs. The PSPICE simulation results of the converter based on 0.25μm CMOS process are presented. The results show that the analysis method is valid and effective.

A novel current-mode versatile filter employing CCCDCC and MO-OTA

This paper proposed a novel second-order versatile filter employing Current Controlled Current Differencing Current Conveyor (CCCDCC) and Multi-Output Operational Transconductance Amplifier (MO-OTA). The proposed filter has a SISO (Single Input Single Output) structure which can serve as low-pass, high-pass, band-pass band-stop and all-pass filter by changing the bias signals. Moreover, both of the frequency and amplitude of the filter can be adjusted electronically. The PSPICE simulation results of the proposed filter based on 0.25μm CMOS process are presented; the results show that the analysis method is valid and effective.

Ultra-low noise and high PSR LDO design

This paper presents a new ultra-low noise and high PSR LDO structure. This structure can achieve ultra-low noise performance without large filter capacitor by incorporating a capacitance amplifying circuit in the structure of LDO with pre-regulation. A large amount of chip area will be saved in this structure. Also this structure can achieve high PSR under a wide frequency range by introducing a feed-forward path between the drain and gate of the pass transistor. A novel LDO in proposed structure is realized under SMIC 0.18μm process. The experimental results show that proposed LDO structure can achieve a total output noise of 25.5μV between 10Hz-1KHz and 56.4μV between 1KHz-1MHz with a filter capacitor of 5pF. PSR is -71.6dB under low frequency until 49KHz and at least -65.7dB under entire frequency range.

A 1575.42MHz High Frequency Accuracy CMOS Quadrature LC-VCO for GPS on Chip Application

A 1575.42MHz quadrature LC-VCO (QVCO) was presented for GPS on-chip application. Bimodal oscillation behavior inherent to the QVCO was analyzed and a voltage controlled RC phase shifter (VCPS) was proposed which effectively eliminated bimodal oscillation. The simulation results under mixed-signal 0.18um 1P6M process showed that this novel oscillator with VCPS achieved 10-5 frequency accuracy at 1575.42MHz, exhibited a phase noise of-110dBc/Hz at 1MHz offset frequency from a 1575.42MHz center frequency, dissipated only 25.9mW at 1.8V DC supply, and have very small amplitude attenuation.

A new frequency compensation scheme for current-mode DC/DC converter

This paper presents a new frequency compensation scheme for current-mode DC/DC converters. The proposed compensation scheme includes the miller capacitance control unit and dynamic zero control unit. The miller capacitance control unit uses a small compensated capacitance Cm to establish a big capacitance. Therefore, the systems transient response is improved as the fast charge or discharges on the small on-chip capacitance Cm. The dynamic zero control unit uses a NMOS which operates in triode region to act as a voltage controlled linear resistor. As the control voltage varies with the load current, it will generate a dynamic zero to cancel the pole ω1. Therefore, the systems stability is great ly improved. Simulated in a 0.18-µm CMOS process, the proposed compensation scheme achieves full range alternating current stability from 0 to 450mA load current and improves the transient response with 150mV voltage variation and 10µS settling time for a 250mA load step.

An inductorless CMOS LNA with single input and differential output

This paper presents a design technique of an inductorless CMOS LNA with single-ended input and differential output. Its main amplifier circuit exploits a non-inverting cascode common gate path and an inverting cascode common source path to realize the balun function. No inductor is used in the input impendence match. The noise contribution of components is represented by equivalent current and voltage sources and analyzed for minimization methods. The proposed LNA is processed in a RF 0.18µm CMOS process. With the proposed techniques, the LNA features NF 2.88dB, S11 −20.1dB, voltage gain 21.1dB, P1dB −12.9dBm at 1.575GHz.