Jingwei Bai

High speed graphene transistors with a self-aligned nanowire gate

Graphene has attracted considerable interest as a potential new electronic material. With its high carrier mobility, graphene is of particular interest for ultrahigh-speed radio-frequency electronics. However, conventional device fabrication processes cannot readily be applied to produce high-speed graphene transistors because they often introduce significant defects into the monolayer of carbon lattices and severely degrade the device performance. Here we report an approach to the fabrication of high-speed graphene transistors with a self-aligned nanowire gate to prevent such degradation. A Co2Si–Al2O3 core–shell nanowire is used as the gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. The physical assembly of the nanowire gate preserves the high carrier mobility in graphene, and the self-alignment process ensures that the edges of the source, drain and gate electrodes are automatically and precisely positioned so that no overlapping or significant gaps exist between these electrodes, thus minimizing access resistance. It therefore allows for transistor performance not previously possible. Graphene transistors with a channel length as low as 140 nm have been fabricated with the highest scaled on-current (3.32 mA μm−1) and transconductance (1.27 mS μm−1) reported so far. Significantly, on-chip microwave measurements demonstrate that the self-aligned devices have a high intrinsic cut-off (transit) frequency of fT = 100–300 GHz, with the extrinsic fT (in the range of a few gigahertz) largely limited by parasitic pad capacitance. The reported intrinsic fT of the graphene transistors is comparable to that of the very best high-electron-mobility transistors with similar gate lengths.

Plasmon resonance enhanced multicolour photodetection by graphene

Graphene has the potential for high-speed, wide-band photodetection, but only with very low external quantum efficiency and no spectral selectivity. Here we report a dramatic enhancement of the overall quantum efficiency and spectral selectivity that enables multicolour photodetection, by coupling graphene with plasmonic nanostructures. We show that metallic plasmonic nanostructures can be integrated with graphene photodetectors to greatly enhance the photocurrent and external quantum efficiency by up to 1,500%. Plasmonic nanostructures of variable resonance frequencies selectively amplify the photoresponse of graphene to light of different wavelengths, enabling highly specific detection of multicolours. Being atomically thin, graphene photodetectors effectively exploit the local plasmonic enhancement effect to achieve a significant enhancement factor not normally possible with traditional planar semiconductor materials.

Rational Fabrication of Graphene Nanoribbons Using a Nanowire Etch Mask

We report a rational approach to fabricate graphene nanoribbons (GNRs) with sub-10 nm width by employing chemically synthesized nanowires as the physical protection mask in oxygen plasma etch. Atomic force microscopy study shows that the patterns of the resulted nanoribbons replicate exactly those of mask nanowires so that ribbons or branched or crossed graphene nanostructures can be produced. Our study shows a linear scaling relation between the resulted GNR widths and mask nanowire diameters with variable slopes for different etching times. GNRs with controllable widths down to 6 nm have been demonstrated. We have fabricated GNR field effect transistors (FETs) with nanoribbons directly connected to bulk graphene electrodes. Electrical measurements on an 8 nm GNR-FET show room temperature transistor behavior with an on/off ratio around 160, indicating appreciable band gaps arise due to lateral confinement. We find the on/off ratio in the log scale inversely scales with ribbon width. This approach opens a new avenue to graphene nanoribbons and other graphene nanostructures in the deep nanometer regime without sophisticated lithography. It thus opens exciting new opportunities for graphene nanodevice engineering.

Very large magnetoresistance in graphene nanoribbons

Graphene has unique electronic properties1,2 and graphene nanoribbons are of particular interest because they exhibit a conduction band gap, which arises due to size confinement and edge effects3-11. Theoretical studies have suggested that graphene nanoribbons could have interesting magneto-electronic properties with very large magnetoresistance predicted4,12-20. Here we report the experimental observation of a significant enhancement in the conductance of a graphene nanoribbon field-effect transistor in a perpendicular magnetic field. A negative magnetoresistance of nearly 100% was observed at low temperatures, with over 50% remaining at room temperature. This magnetoresistance can be tuned by varying the gate or source-drain bias. We also find that the charge transport in the nanoribbons is not significantly modified by an in-plane magnetic field. The large values of the magnetoresistance we observe may be attributed to the reduction of quantum confinement by the formation of cyclotron orbits and the delocalization effect under the perpendicular magnetic field15-20.

High-frequency self-aligned graphene transistors with transferred gate stacks

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits.

Sub-100 nm channel length graphene transistors

Here we report high-performance sub-100 nm channel length graphene transistors fabricated using a self-aligned approach. The graphene transistors are fabricated using a highly doped GaN nanowire as the local gate with the source and drain electrodes defined through a self-aligned process and the channel length defined by the nanowire size. This fabrication approach allows the preservation of the high carrier mobility in graphene and ensures nearly perfect alignment between source, drain, and gate electrodes. It therefore affords transistor performance not previously possible. Graphene transistors with 45-100 nm channel lengths have been fabricated with the scaled transconductance exceeding 2 mS/μm, comparable to the best performed high electron mobility transistors with similar channel lengths. Analysis of and the device characteristics gives a transit time of 120-220 fs and the projected intrinsic cutoff frequency (f(T)) reaching 700-1400 GHz. This study demonstrates the exciting potential of graphene based electronics in terahertz electronics.

High-κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors

Deposition of high-κ dielectrics onto graphene is of significant challenge due to the difficulties of nucleating high quality oxide on pristine graphene without introducing defects into the monolayer of carbon lattice. Previous efforts to deposit high-κ dielectrics on graphene often resulted in significant degradation in carrier mobility. Here we report an entirely new strategy to integrate high quality high-κ dielectrics with graphene by first synthesizing freestanding high-κ oxide nanoribbons at high temperature and then transferring them onto graphene at room temperature. We show that single crystalline Al2O3 nanoribbons can be synthesized with excellent dielectric properties. Using such nanoribbons as the gate dielectrics, we have demonstrated top-gated graphene transistors with the highest carrier mobility (up to 23,600 cm2/V·s) reported to date, and a more than 10-fold increase in transconductance compared to the back-gated devices. This method opens a new avenue to integrate high-κ dielectrics on graphene with the preservation of the pristine nature of graphene and high carrier mobility, representing an important step forward to high-performance graphene electronics.

Top-gated graphene nanoribbon transistors with ultrathin high-k dielectrics.

The integration ultrathin high dielectric constant (high-k) materials with graphene nanoribbons (GNRs) for top-gated transistors can push their performance limit for nanoscale electronics. Here we report the assembly of Si/HfO(2) core/shell nanowires on top of individual GNRs as the top-gates for GNR field-effect transistors with ultrathin high-k dielectrics. The Si/HfO(2) core/shell nanowires are synthesized by atomic layer deposition of the HfO(2) shell on highly doped silicon nanowires with a precise control of the dielectric thickness down to 1-2 nm. Using the core/shell nanowires as the top-gates, high-performance GNR transistors have been achieved with transconductance reaching 3.2 mS microm(-1), the highest value for GNR transistors reported to date. This method, for the first time, demonstrates the effective integration of ultrathin high-k dielectrics with graphene with precisely controlled thickness and quality, representing an important step toward high-performance graphene electronics.

Single crystalline PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices.

We report the formation of PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices from such heterostructures. Scanning electron microscopy studies show that silicon nanowires can be converted into PtSi nanowires through controlled reactions between lithographically defined platinum pads and silicon nanowires. High-resolution transmission electron microscopy studies show that PtSi/Si/PtSi heterostructure has an atomically sharp interface with epitaxial relationships of Si[110]//PtSi[010] and Si(111)//PtSi(101). Electrical measurements show that the pure PtSi nanowires have low resistivities approximately 28.6 microOmega.cm and high breakdown current densities>1x10(8) A/cm2. Furthermore, using single crystal PtSi/Si/PtSi nanowire heterostructures with atomically sharp interfaces, we have fabricated high-performance nanoscale field-effect transistors from intrinsic silicon nanowires, in which the source and drain contacts are defined by the metallic PtSi nanowire regions, and the gate length is defined by the Si nanowire region. Electrical measurements show nearly perfect p-channel enhancement mode transistor behavior with a normalized transconductance of 0.3 mS/microm, field-effect hole mobility of 168 cm2/V.s, and on/off ratio>10(7), demonstrating the best performing device from intrinsic silicon nanowires.

High-Performance Top-Gated Graphene-Nanoribbon Transistors Using Zirconium Oxide Nanowires as High-Dielectric-Constant Gate Dielectrics

Graphene has attracted a great deal of interest in the past several years.[1–5] New physics has been predicted and observed, such as ultrahigh carrier mobility,[6] electron-hole symmetry and quantum hall effect,[2, 4, 7–9] and the strong suppression of weak localization.[10–12] For mainstream logic application, graphene nanoribbons (GNRs), as thin strips of graphene or unrolled carbon nanotubes, are predicted to be semiconducting due to edge effects and quantum confinement.[13–15] Recent experimental studies have also demonstrated that GNRs can effectively function as a semiconducting channel for room-temperature field-effect transistors.[16–22] By varying the width of GNRs at selected points, it is also possible to create graphene quantum dots within a GNR for single electron transistors.[23] These studies represent important advances in GNR based electronics. However, most of the efforts to date employ a silicon substrate as a global back gate and silicon oxide as the gate dielectrics. While such a device has led to many interesting scientific discoveries, it will be of limited use for practical applications due to the high gate switching voltage required and the inability to independently address multiple units on the same chip.[17, 20, 21] Top-gated devices with high-k dielectrics can significantly reduce the required switching voltage and allow independently addressable device arrays and functional circuits, and therefore are of significant interest.