Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Jinhai Shao is active.

Publication


Featured researches published by Jinhai Shao.


ACS Applied Materials & Interfaces | 2015

Subwavelength Gold Grating as Polarizers Integrated with InP-Based InGaAs Sensors

Rui Wang; Tao Li; Xiumei Shao; Xue Li; Xiaqi Huang; Jinhai Shao; Yifang Chen; Haimei Gong

There are currently growing needs for polarimetric imaging in infrared wavelengths for broad applications in bioscience, communications and agriculture, etc. Subwavelength metallic gratings are capable of separating transverse magnetic (TM) mode from transverse electric (TE) mode to form polarized light, offering a reliable approach for the detection in polarization way. This work aims to design and fabricate subwavelength gold gratings as polarizers for InP-based InGaAs sensors in 1.0-1.6 μm. The polarization capability of gold gratings on InP substrate with pitches in the range of 200-1200 nm (fixed duty cycle of 0.5) has been systematically studied by both theoretical modeling with a finite-difference time-domain (FDTD) simulator and spectral measurements. Gratings with 200 nm lines/space in 100-nm-thick gold have been fabricated by electron beam lithography (EBL). It was found that subwavelength gold gratings directly integrated on InP cannot be applied as good polarizers, because of the existence of SPP modes in the detection wavelengths. An effective solution has been found by sandwiching the Au/InP bilayer using a 200 nm SiO2 layer, leading to significant improvement in both TM transmission and extinction ratio. At 1.35 μm, the improvement factors are 8 and 10, respectively. Therefore, it is concluded that the Au/SiO2/InP trilayer should be a promising candidate of near-infrared polarizers for the InP-based InGaAs sensors.


Nanotechnology | 2016

Photon nanojet lens: Design, fabrication and characterization

Chen Xu; Sichao Zhang; Jinhai Shao; Bing-Rui Lu; Reyad Mehfuz; Stacey Drakeley; Fumin Huang; Yifang Chen

In this paper, a novel nanolens with super resolution, based on the photon nanojet effect through dielectric nanostructures in visible wavelengths, is proposed. The nanolens is made from plastic SU-8, consisting of parallel semi-cylinders in an array. This paper focuses on the lens designed by numerical simulation with the finite-difference time domain method and nanofabrication of the lens by grayscale electron beam lithography combined with a casting/bonding/lift-off transfer process. Monte Carlo simulation for injected charge distribution and development modeling was applied to define the resultant 3D profile in PMMA as the template for the lens shape. After the casting/bonding/lift-off process, the fabricated nanolens in SU-8 has the desired lens shape, very close to that of PMMA, indicating that the pattern transfer process developed in this work can be reliably applied not only for the fabrication of the lens but also for other 3D nanopatterns in general. The light distribution through the lens near its surface was initially characterized by a scanning near-field optical microscope, showing a well defined focusing image of designed grating lines. Such focusing function supports the great prospects of developing a novel nanolithography based on the photon nanojet effect.


international conference on solid state and integrated circuits technology | 2006

A novel high-k gate dielectric HfLaO for next generation CMOS technology

M. F. Li; X.P. Wang; Hao Yu; Chunxiang Zhu; Albert Chin; A.Y. Du; Jinhai Shao; W. Lu; X.C. Shen; Patricia M. Liu; Steven Hung; Patrick Lo; D. L. Kwong

The physical and electrical characteristics of high-k (HK) gate dielectric HfLaO were systematically investigated. Incorporation of La in HfO2 can raise the film crystallization temperature from 400degC to 900degC. Moreover, NMOSFETs fabricated with HfLaO gate dielectric exhibit superior electrical performances in terms of threshold voltage (Vth), bias temperature instability (BTI), channel electron mobility and gate leakage current compared to those fabricated with HfO2 dielectric. Particularly, the authors also report that the effective work function (EWF) of metal gate (MG) can be tuned to a wide enough range to fulfil the requirement of bulk CMOSFETs by employing HfLaO dielectric and n- and p-type metal gates respectively. These advantages are correlated to the enhanced thermal stability and reduction of oxygen vacancy density in HfLaO compared to HfO2, making it a promising high-k gate dielectric to replace SiO2 and SiON to meet the ITRS requirements. Finally, a possible dual metal gate CMOS integration process is proposed


Applied Optics | 2015

Simulation and experimental study of aspect ratio limitation in Fresnel zone plates for hard-x-ray optics.

Jianpeng Liu; Jinhai Shao; Sichao Zhang; Yaqi Ma; Nit Taksatorn; Chengwen Mao; Yifang Chen; Biao Deng; Tiqiao Xiao

For acquiring high-contrast and high-brightness images in hard-x-ray optics, Fresnel zone plates with high aspect ratios (zone height/zone width) have been constantly pursued. However, knowledge of aspect ratio limits remains limited. This work explores the achievable aspect ratio limit in polymethyl methacrylate (PMMA) by electron-beam lithography (EBL) under 100 keV, and investigates the lithographic factors for this limitation. Both Monte Carlo simulation and EBL on thick PMMA are applied to investigate the profile evolution with exposure doses over 100 nm wide dense zones. A high-resolution scanning electron microscope at low acceleration mode for charging free is applied to characterize the resultant zone profiles. It was discovered for what we believe is the first time that the primary electron-beam spreading in PMMA and the proximity effect due to extra exposure from neighboring areas could be the major causes of limiting the aspect ratio. Using the optimized lithography condition, a 100 nm zone plate with aspect ratio of 15/1 was fabricated and its focusing property was characterized at the Shanghai Synchrotron Radiation Facility. The aspect ratio limit found in this work should be extremely useful for guiding further technical development in nanofabrication of high-quality Fresnel zone plates.


Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena | 2014

Multistep Aztec profiles by grayscale electron beam lithography for angle-resolved microspectrometer applications

Sichao Zhang; Jinhai Shao; Jianpeng Liu; Chen Xu; Yaqi Ma; Yifang Chen; Nit Taksatorn; Yan Sun

In this paper, grayscale electron beam lithography is applied to generate multistep Aztec profiles (MAPs) for angle-resolved spectral applications such as microspectrometers. Monte Carlo simulations taking into consideration the proximity effect are carried out to calculate the spatial dose distributions for desired profiles, using actual dissolution rates measured on the same resist. The MAPs in PMMA resist with step heights from 50 to 200 nm and step widths from 0.1 to 5 μm are achieved by high-resolution electron beam lithography, and high-resolution scanning electron microscopy and atomic force microscopy are used to characterize the quality of the MAPs. Angle-resolved spectra of the reflectance are obtained using a finite-difference time-domain simulator and by experimental measurements. A distinct angle selection of the wavelengths is demonstrated, though the high surface roughness measured on the deeper steps may cause broadening of the spectral peaks. Initial investigations into the origin of the ...


IEEE Electron Device Letters | 2016

Investigation of Traps at MoS 2 /Al 2 O 3 Interface in nMOSFETs by Low-Frequency Noise

Hui-Wen Yuan; Hui Shen; Jun-Jie Li; Jinhai Shao; Daming Huang; Yifang Chen; Pengfei Wang; Shi-Jin Ding; Wen-Jun Liu; Albert Chin; M. F. Li

A new method is proposed to distinguish the contributions of the low-frequency noise (LFN) from the channel and the source/drain Schottky contacts in MOS devices. The method is applied to back-gated nMOSFETs with MoS<sub>2</sub> channel and Al<sub>2</sub>O<sub>3</sub> gate dielectric. To avoid a possible noise signal contamination from the top MoS<sub>2</sub> surface by oxygen or water molecules absorption, the nMOSFETs with multilayer MoS<sub>2</sub> are fabricated, and the measurements are carried out in the vacuum. The trap density Not at the MoS<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub> interface is derived for the first time using the proposed method. It is found that the Not responsible to LFN depends strongly on the surface potential, ranging from 4 × 10<sup>10</sup> cm<sup>-2</sup> in the weak over-drive region to 5 × 10<sup>11</sup> cm<sup>-2</sup> in the strong over-drive region.


Journal of Micro-nanolithography Mems and Moems | 2017

Nanofabrication of 10-nm T-shaped gates using a double patterning process with electron beam lithography and dry etch

Jinhai Shao; Jianan Deng; W. Lu; Yifang Chen

Abstract. A process to fabricate T-shaped gates with the footprint scaling down to 10 nm using a double patterning procedure is reported. One of the keys in this process is to separate the definition of the footprint from that for the gate-head so that the proximity effect originated from electron forward scattering in the resist is significantly minimized, enabling us to achieve as narrow as 10-nm foot width. Furthermore, in contrast to the reported technique for 10-nm T-shaped profile in resist, this process utilizes a metallic film with a nanoslit as an etch mask to form a well-defined 10-nm-wide foot in a SiNx layer by reactive ion etch. Such a double patterning process has demonstrated enhanced reliability. The detailed process is comprehensively described, and its advantages and limitations are discussed. Nanofabrication of InP-based high-electron-mobility transistors using the developed process for 10- to 20-nm T-shaped gates is currently under the way.


ieee international conference on solid state and integrated circuit technology | 2016

Trapping and detrapping of oxide border traps in Al2O3 gate dielectric in MoS2 n-MOSFETs under PBTI stress

Hui-Wen Yuan; Hui Shen; Jun-Jie Li; Jinhai Shao; Daming Huang; Yifang Chen; Pengfei Wang; Shao-Feng Ding; Albert Chin; M. F. Li

In this paper, we report the positive bias temperature instability (PBTI) effects of the back-gated MoS2 n-MOSFET with Al2O3 gate dielectric. Multilayer MoS2 was used and all measurements are carried in vacuum to avoid the electric signal contamination by the top MoS2 surface water or oxygen molecules absorption. In the stress phase, the Id-Vg curve shifts to the positive gate bias direction. In the recovery phase, the Id-Vg shifts back completely to the fresh device curve. This indicates that voltage shift is purely due to trapping or detrapping of the oxide border traps at the MoS2/Al2O3 interface and no new traps are generated during the stress time. When applying different stress voltage and measuring the Id-Vg shift, we can calculate the oxide border trap energy density Ξ(E), which has a peak value of 6×1013cm−2eV−1 at 0.035eV above EC of MoS2 conduction band.


Microelectronic Engineering | 2016

Processing study of SU-8 pillar profiles with high aspect ratio by electron-beam lithography

Yaqi Ma; Yifan Xia; Jianpeng Liu; Sichao Zhang; Jinhai Shao; Bing-Rui Lu; Yifang Chen


Microelectronic Engineering | 2015

Y shape gate formation in single layer of ZEP520A using 3D electron beam lithography

Jinhai Shao; Sichao Zhang; Jianpeng Liu; Bing-Rui Lu; Nit Taksatorn; W. Lu; Yifang Chen

Collaboration


Dive into the Jinhai Shao's collaboration.

Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar

Albert Chin

National Chiao Tung University

View shared research outputs
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Researchain Logo
Decentralizing Knowledge