Jinjuan Xiang

Band alignment of HfO2 on SiO2/Si structure

Band alignment of HfO2 with various thicknesses on SiO2/Si structure is investigated by x-ray photoelectron spectroscopy (XPS). Band bending of HfO2/SiO2/Si system is found to vary with HfO2 thickness. Band alignment of entire HfO2/SiO2/Si is demonstrated using concepts of interfacial or surface gap states and charge neutrality level (CNL). The XPS results are interpreted and attributed to lower CNL of HfO2 than SiO2/Si which induces electron transfer from SiO2/Si to HfO2, resulting in band bending upward for SiO2/Si. These further confirm feasibility of gap state based theory in investigating band alignments of oxide/semiconductor and oxide/oxide interfaces.

Reexamination of band offset transitivity employing oxide heterojunctions

Band offset transitivity is reexamined extendedly by employing oxide heterojuctions. The valence band offsets (ΔEV) at HfO2/SiO2, Al2O3/SiO2, and HfO2/Al2O3 heterojunctions are experimentally determined to be 0.81, 0.25, and 0.25 eV, respectively, by X-ray photoelectron spectroscopy. Thus, the ΔEV at HfO2/Al2O3 heterojunction is not equal to the ΔEV at HfO2/SiO2 minus the ΔEV at Al2O3/SiO2 heterostructures (0.25 ≠ 0.81 − 0.25 = 0.56), i.e., the transitivity rule fails for oxide heterojunctions. Different distributions of interfacial induced gap states at the three heterostructures contribute to this failure of transitivity rule.

A possible origin of core-level shift in SiO2/Si stacks

Band alignments of SiO2/Si stacks with different SiO2 thicknesses are re-examined by X-ray photoelectron spectroscopy (XPS) and X-ray Auger electron spectroscopy. The energy difference between core-levels of SiO2 and Si is found to decrease with thicker SiO2. A possible explanation based on surface gap states (SGS) and charge neutrality level (CNL) is proposed to elucidate band alignment of SiO2/Si. Due to lower CNL of SiO2 SGS than Fermi level of Si, electrons transfer from Si to SiO2 SGS. With thicker SiO2 fewer electrons transfer from Si to SiO2, resulting in larger potential drop across SiO2 and XPS results.

Growth mechanism of atomic-layer-deposited TiAlC metal gate based on TiCl4 and TMA precursors*

TiAlC metal gate for the metal-oxide-semiconductor field-effect-transistor (MOSFET) is grown by the atomic layer deposition method using TiCl4 and Al(CH3)3(TMA) as precursors. It is found that the major product of the TiCl4 and TMA reaction is TiAlC, and the components of C and Al are found to increase with higher growth temperature. The reaction mechanism is investigated by using x-ray photoemission spectroscopy (XPS), Fourier transform infrared spectroscopy (FTIR), and scanning electron microscope (SEM). The reaction mechanism is as follows. Ti is generated through the reduction of TiCl4 by TMA. The reductive behavior of TMA involves the formation of ethane. The Ti from the reduction of TiCl4 by TMA reacts with ethane easily forming heterogenetic TiCH2, TiCH=CH2 and TiC fragments. In addition, TMA thermally decomposes, driving Al into the TiC film and leading to TiAlC formation. With the growth temperature increasing, TMA decomposes more severely, resulting in more C and Al in the TiAlC film. Thus, the film composition can be controlled by the growth temperature to a certain extent.

FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin

The large parasitic resistance has become a critical limiting factor to on current (ION) of FinFET and nanowire devices. Fully metallic source and drain (MSD) process is one of the most promising solutions but it often suffers from intolerant junction leakage in bulk FETs. In this paper, fully MSD process on fin-on-insulator (FOI) FinFET is investigated extensively for the first time. By forming fully Ni(Pt) silicide on physically isolated fins, about 90% reduction in contacted resistivities (Rcs) and 55% reduction in sheet resistances (Rss) are achieved without obvious junction leakage degradation. As a consequence, Ion of transistor, with gate length (Lg) of 20nm, is increased 30 times, up to 547μA/μm for NMOS and 324 μA/μm for PMOS, respectively. Excellent controls of SCE and channel leakage with 47% DIBL, 32% SS and 2.5% device leakages reductions over the counterpart of conventional bulk FinFETs are also obtained. Meanwhile, the fully MSD process induces clear tensile stress into narrow fin-channel, resulting in enhanced electron mobility in NMOS. A further improvement in PMOS drive ability (486μA/μm) by using Schottky barrier source and drain (SBSD) technology is also explored.

Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs

Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate (HK/MG) process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer (PTSL) and source drain extension (SDE) doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function (EWF) MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the devices scaling.

Ion-Implanted TiN Metal Gate With Dual Band-Edge Work Function and Excellent Reliability for Advanced CMOS Device Applications

This paper proposed, for the first time, that the dual band-edge effective work functions are achieved by employing a single metal gate (MG) and single high-k (HK) dielectric via ion implantation into a TiN MG for HP CMOS device applications under a gate-last process flow. The P/BF2 ion-implanted TiN/HfO2/ILSiO2 gate-stack does not degrade the gate leakage, reliability, and carrier mobility, and reduces the effective oxide thickness. The impact of P/BF2 ion implant energy, dose, and TiN gate thickness on the properties of implanted TiN/HfO2/ILSiO2 gate-stack is studied, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the replacement MG and HK/MG last process flow to fabricate HP CMOSFETs and CMOS 32 frequency dividers with a minimum gate length of 25 nm.

Band alignment of TiN/HfO2 interface of TiN/HfO2/SiO2/Si stack

Band alignment of TiN/HfO2 interface of TiN/HfO2/SiO2/Si stack is investigated by x-ray photoelectron spectroscopy (XPS). The p-type Schottky barrier height (p-SBH) is found to increase with thicker HfO2 thickness. Since considering only the metal/dielectric interface cannot explain this phenomenon, band alignment of TiN/HfO2 interface of TiN/HfO2/SiO2/Si stack is demonstrated based on band alignment of entire gate stack. Dependence of p-SBH on HfO2 thickness is interpreted and contributed to fixed charges in gate stack, interfacial gap state charges at HfO2/SiO2 interface, and space charges in Si substrate. Electrical measurements of capacitor structures further support XPS results and corresponding explanation.

Crystallization behaviors of ultrathin Al-doped HfO2 amorphous films grown by atomic layer deposition

In this work, ultrathin pure HfO2 and Al-doped HfO2 films (about 4-nm thick) are prepared by atomic layer deposition and the crystallinities of these films before and after annealing at temperatures ranging from 550 °C to 750 °C are analyzed by grazing incidence x-ray diffraction. The as-deposited pure HfO2 and Al-doped HfO2 films are both amorphous. After 550-°C annealing, a multiphase consisting of a few orthorhombic, monoclinic and tetragonal phases can be observed in the pure HfO2 film while the Al-doped HfO2 film remains amorphous. After annealing at 650 °C and above, a great number of HfO2 tetragonal phases, a high-temperature phase with higher dielectric constant, can be stabilized in the Al-doped HfO2 film. As a result, the dielectric constant is enhanced up to about 35. The physical mechanism of the phase transition behavior is discussed from the viewpoint of thermodynamics and kinetics.

Remote interfacial dipole scattering and electron mobility degradation in Ge field-effect transistors with GeO x /Al2O3 gate dielectrics

Remote Coulomb scattering (RCS) on electron mobility degradation is investigated experimentally in Ge-based metal-oxide-semiconductor field-effect-transistors (MOSFETs) with GeOx/Al2O3 gate stacks. It is found that the mobility increases with greater GeOx thickness (7.8-20.8 angstrom). The physical origin of this mobility dependence on GeOx thickness is explored. The following factors are excluded: Coulomb scattering due to interfacial traps at GeOx/Ge, phonon scattering, and surface roughness scattering. Therefore, the RCS from charges in gate stacks is studied. The charge distributions in GeOx/Al2O3 gate stacks are evaluated experimentally. The bulk charges in Al2O3 and GeOx are found to be negligible. The density of the interfacial charge is + 3.2 x 10(12) cm(-2) at the GeOx/Ge interface and -2.3 x 10(12) cm(-2) at the Al2O3/GeOx interface. The electric dipole at the Al2O3/GeOx interface is found to be + 0.15 V, which corresponds to an areal charge density of 1.9 x 10(13) cm(-2). The origin of this mobility dependence on GeOx thickness is attributed to the RCS due to the electric dipole at the Al2O3/GeOx interface. This remote dipole scattering is found to play a significant role in mobility degradation. The discovery of this new scattering mechanism indicates that the engineering of the Al2O3/GeOx interface is key for mobility enhancement and device performance improvement. These results are helpful for understanding and engineering Ge mobility enhancement.