Jinoo Joung

Overview of ITU-T NGN QoS Control

This article presents an overview of standards activities defining the QoS control architecture. Several standards bodies define the QoS control architectures based on their scope of work. This article first reviews the QoS control architectures defined in the standards bodies such as Cable Lab, DSL Forum, MSF, ETSI, and ITU-T. ITU-T NGN architecture provides the generic framework to cover the results of each standards body. Other architectures focus on solving specific problems. We explain in more detail the ITU-T QoS control architecture defined in resource and admission control functions (RACF) and discuss future standards developments.

IEEE 802.1 AVB and Its Application in Carrier-Grade Ethernet [Standards Topics]

Ethernet is increasingly being used in carrier networks to transport real-time traffic, including wireless backhaul network traffic, time-sensitive audio/video applications in access networks, and circuit emulation for legacy services. With the replacement of traditional circuit-switched networks with Ethernet-based packet networks, it must be ensured that the application timing and QoS requirements are met. The IEEE 802.1 Audio/Video Bridging Task Group is developing a comprehensive set of standards to enable high quality, low-latency streaming of time-sensitive applications. These standards specify a means of providing time synchronization (IEEE 802.IAS), a resource reservation protocol (IEEE 802.1Qat), and a set of forwarding and queuing rules that bound the variability of delay in an AVB network (IEEE 802.1Qav). These standards are described, including their potential application to carrier-grade Ethernet networks.

Performance measures and scheduling policies in ring networks

A unidirectional ring network is considered. A node may transmit at most one packet per slot to its downstream neighbor. Potentially all nodes may transmit at the same slot. The achievable performance is studied and policies are proposed for both the evacuation mode and continual operation. In the evacuation mode each node has initially an amount of packets destined for every other node of the ring, and no more packets are generated later. It is shown that the furthest destination first (FDF) policy, that gives priority to the packet with the longest way to go at each node, minimizes the time until every packet reaches its destination. Furthermore it is shown that the closest destination first (CDF) policy, that gives priority to the packet with the shortest way to go at each node, minimizes the average packet delivery time. A formula for the optimal evacuation time is obtained. The continual operation of the ring is considered then where packets are generated according to some arrival process. For any arrival sample path, the PDF maximizes the fraction of the time at which the ring is empty. The performance analysis of individual origin-destination traffic streams under FDF is facilitated based on the following. For each traffic stream, a single server priority queue is identified such that the average sojourn time of the traffic stream in the ring is equal to the aggregate transmission time plus the queueing delay of the low priority stream in the queue. Formulas for the sojourn time are obtained for iid arrivals. The performance of CDF and FIFO in continual operation is studied by simulation. It turns out that the CDF, minimum delay policy for the evacuation, has the worst performance in continual operation. >

Fast packet classification using field-level trie

Packet classification plays an important role in next-generation Internet routers in providing various services such as packet filtering, policy routing, traffic policing, and load balancing. In this paper, we propose an original field-level trie classification (FLTC) scheme that accommodates classifier (rule database) with multiple fields specified in different forms (prefix and range). The FLTC achieves a high classification speed with reasonable storage. It is also highly scalable regarding the size and the number of fields of classifiers.

Scalable Packet Classification through Maximum Entropy Hashing

In this paper we propose a new packet classification algorithm, which can substantially improve the performance of a classifier by decreasing the rulebase lookup latency. The algorithm hierarchically partitions the rulebase into smaller independent sub-rulebases by employing hashing. By using the same hash key used in the partitioning a classifier only needs to look up the relevant sub-rulebase to which an incoming packet belongs. For an optimal partitioning of rulebases, we apply the notion of maximum entropy to the hash key selection. We performed the detailed simulations of our proposed algorithm on synthetic rulebases of size IK to 500K entries using real packet traces. The results show that the algorithm can significantly outperform existing classifiers by reducing the size of a rulebase by more than four orders of magnitude with just two-levels of partitioning. Both the space and time complexity of the algorithm exhibit linearity in terms of the size of a rulebase, suggesting a good scalable solution for the packet classification with a large rulebase.

Exploiting parallelism in memory operations for code optimization

Code size reduction is ever becoming more important for compilers targeting embedded processors because these processors are often severely limited by storage constraints and thus the reduced code size can have a positively significant impact on their performance. Various code size reduction techniques have different motivations and a variety of application contexts utilizing special hardware features of their target processors. In this work, we propose a novel technique that fully utilizes a set of hardware instructions, called the multiple load/store (MLS) or parallel load/store (PLS), that are specially featured for reducing code size by minimizing the number of memory operations in the code. To take advantage of this feature, many microprocessors support the MLS instructions, whereas no existing compilers fully exploit the potential benefit of these instructions but only use them for some limited cases. This is mainly because optimizing memory accesses with MLS instructions for general cases is an NP-hard problem that necessitates complex assignments of registers and memory offsets for variables in a stack frame. Our technique uses a couple of heuristics to efficiently handle this problem in a polynomial time bound.