Jinyang Li

Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration

Solar-powered sensor nodes with energy storages are widely used today and promising in the coming trillion sensor era, as they do not require manual battery charging or replacement. The changeable and limited solar power supply seriously affects the deadline miss rates (DMRs) of tasks on these nodes and therefore energy-driven task scheduling is necessary. However, current algorithms focus on the single period (or the current task queue) for high energy utilization and suffer from bad long term DMR. To get better long term DMR, we propose a long term deadline-aware scheduling algorithm with energy migration strategies for distributed super capacitors. Experimental results show that the proposed algorithm reduces the DMR by 27.8% and brings less than 3% of the total energy consumption.

Solar Power Prediction Assisted Intra-task Scheduling for Nonvolatile Sensor Nodes

With the advent of the era of trillion sensors, solar-powered sensor nodes are widely used as they do not require battery charging or replacement. However, the limited and intermittent solar energy supply seriously affects deadline miss rate (DMR) of tasks. Furthermore, traditional solar-powered sensor nodes also suffer from energy loss of battery charging and voltage conversion. Recently, a storage-less and converter-less power supply architecture has been proposed to achieve higher energy efficiency by removing the leaky energy storage and dc voltage conversion. Without energy storages, a node using inter-task scheduling is more sensitive to solar variations, which results in high DMRs. This paper proposes an intra-task scheduling scheme for the storage-less and converter-less solar-powered sensor nodes, whose features include power prediction based on classified solar profiles, a trigger mechanism to select scheduling points, an artificial neural network to calculate task priorities and a fine-grained task selection algorithm. Experimental results show that the proposed algorithm reduces DMR by up to 30% and improves energy utilization efficiency by 20% with trivial energy overheads.

Incidental computing on IoT nonvolatile processors

Batteryless IoT devices powered through energy harvesting face a fundamental imbalance between the potential volume of collected data and the amount of energy available for processing that data locally. However, many such devices perform similar operations across each new input record, which provides opportunities for mining the potential information in buffered historical data, at potentially lower effort, while processing new data rather than abandoning old inputs due to limited computational energy. We call this approach incidental computing, and highlight synergies between this approach and approximation techniques when deployed on a non-volatile processor platform (NVP). In addition to incidental computations, the backup and restore operations in an incidental NVP provide approximation opportunities and optimizations that are unique to NVPs.We propose a variety of incidental approximation approaches suited to NVPs, with a focus on approximate backup and restore, and approximate recomputation in the face of power interruptions. We perform RTL level evaluation for many frequently used workloads. We show that these incidental techniques provide an average of 4.2X more forward progress than precise NVP execution.CCS CONCEPTS• Computer systems organization → Single instruction, multiple data; Special purpose systems; System on a chip; Embedded hardware;

Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead

Nonvolatile processors have manifested strong vitality in battery-less energy harvesting sensor nodes due to their characteristics of zero standby power, resilience to power failures and fast read/write operations. However, I/O and sensing operations cannot store their system states after power off, hence they are sensitive to power failures and high power switching overhead is induced during power oscillation, which significantly degrades the system performance. In this paper, we propose a novel performance-aware task scheduling technique considering power switching overhead for energy harvesting nonvolatile processors. We first give the analysis of the power switching overhead on energy harvesting sensor nodes. Then, the scheduling problem is formulated by MILP (Mixed Integer Linear Programming). Furthermore, a task splitting strategy is adopted to improve the performance and an heuristic scheduling algorithm is proposed to reduce the problem complexity. Experimental results show that the proposed scheduling approach can improve the performance by 14% on average compared to the state-of-the-art scheduling strategy. With the employment of the task splitting approach, the execution time can be further reduced by 10.6%.

CP-FPGA: Energy-Efficient Nonvolatile FPGA With Offline/Online Checkpointing Optimization

Field-programmable gate arrays (FPGAs) have drawn lots of attentions due to their programmability and high performance. Recently, ultralow-power FPGAs for Internet of Things, together with energy-harvesting technique, have become an emerging self-powered computing platform. However, volatile memory in FPGA will lose their states under unstable power supplies and cannot work efficiently. Nonvolatile FPGA becomes a promising alternative. This paper proposes a hardware/software codesign nonvolatile FPGA with efficient offline/online checkpointing strategy (CP-FPGA). Backup energy is reduced by offline selecting proper checkpointing locations to minimize backup data. An online scheduler is further proposed to balance computation rollback overhead against backup energy. Experimental results show that the proposed CP-FPGA reduces 39.5% energy consumption on average compared with the state-of-the-art techniques.

A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving

With an ever-increasing demand for energy efficiency, processors with instant-on and zero leakage features are highly appreciated in energy harvesting as well as “normally off” applications. Recently, zero-standby power and fast switching nonvolatile processors (NVPs) have been proposed based on emerging nonvolatile memories (NVMs), such as ferroelectric RAM or spin-transfer-torque magnetic RAM. However, previous NVPs store all data to NVM upon every power interruption, resulting in high-energy consumption and degraded NVM endurance. This paper presents a 65-nm fully CMOS-logic-compatible ReRAM-based NVP supporting time-space domain adaption. It incorporates adaptive nonvolatile controller, nonvolatile flip-flops, and nonvolatile static random access memory (nvSRAM) with self-write termination. Data redundancy in both time and space domain is fully exploited to reduce store/restore time/energy and boost clock frequency. The NVP operates at >100 MHz and achieves 20 ns/0.45 nJ restore time/energy, realizing >6

> 4\times

\times

Faster Clock Frequency and

and >6000

> 6\times

\times

Higher Restore Speed

higher speed and energy efficiency of restore and >4