Jiren Yuan

Performance analysis of general charge sampling

This paper focuses on the performance analysis of general charge sampling circuits that have been applied in signal capture. The theoretical analysis applies not only for small signal capture, but also for normal signal sampling. Based on a general charge sampling model, the transferring function, together with noise transference, clock jitter tolerance, and clock feedthrough effects, are analysed and compared to conventional voltage sampling. The results show the advantages and limits of charge sampling in circuit design and applications.

Realization of a floating-point A/D converter

A floating-point analog-to-digital converter (FP-ADC) with a linear architecture has been implemented using an amplifier network in front of a pipeline ADC. The amplifier network has outputs with binary weighted gains, each sampled separately. The signal with the proper gain is then converted in the ADC. This structure allows instant floating point exponent determination. The mismatches in the amplifier network has been analyzed and successfully reduced. A prototype FP-ADC is currently being manufactured in a 0.35 /spl mu/m double-poly CMOS process. Post-layout simulations show an operating frequency in excess of 30 MS/s with 74 dB dynamic range and 8 bit resolution.

An 8-Bit, 100-MHz low glitch interpolation DAC

This paper describes an 8-Bit, 100-MHz current steering CMOS low glitch interpolation digital to analog converter (DAC). It includes a 16-tap voltage controlled delay line and 8-Bit based linear interpolators, making the effective clock rate up to 1.6-GHz. With the linear interpolation, the requirement on the analog reconstruction filter is relaxed, and low glitch digital to analog conversion is achieved. The chip is fabricated with a 3.3 V, 0.35 /spl mu/m digital CMOS process.

A programmable analog-to-digital converter

In this paper, a programmable analog-to-digital converter (ADC) is proposed. Based on a flexible switched-capacitor stage, the amplifier and integrator is easily transformed to each other. By manipulating the feed path from the quantizer to the MDAC, the function can be programmed between sigma-delta modulators and pipelined ADCs. At the fixed sampling frequency, the proposed ADC can be programmed for dynamic range, bandwidth and power consumption, which is simple and feasible for a lot of applications, such as programmable components.

A non-feedback multiphase clock generator using direct interpolation

This paper presents a new multiphase clock generator using direct interpolators. No feedback loop is required. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit was fabricated in a standard 0.35 /spl mu/m, 3.3 V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1 GHz.

A low-voltage high-speed sampling technique

A new sampling technique is proposed, which integrates input current instead of tracking input voltage to realize high speed and low voltage sampling. Both the theoretical deduction and the simulation prove the advantages of improving the speed and accuracy of CMOS sampling circuits. A practical charge sampling circuit with 3 V supply, 500 MS/s and 9-bit accuracy is suggested.

A 10-bit 500-MS/s 124-mW Subranging Folding ADC in 0.13 μm CMOS

A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (≫250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Spectre simulation in a digital 0.13μm CMOS process. The chip occupies an active area of 0.54mm2

Design considerations of a floating-point ADC with embedded S/H

This paper presents the implementation and test results of a 10+5 bit 50 MS/s floating-point ADC, along with the design considerations. The combination of resistive weighting with identical chopped gain stages proved successful in gain, delay and offset matching. It demonstrated that the input referred thermal noise of the gain stages needs to aim for 15 bits, while the rest of the requirements such as channel matching (gain, delay, offset) and settling time need only 10 bits. The channel selecting logic has a serious impact on the ADC distortion, especially at high frequencies. For this reason, a robust channel selecting logic is suggested.

A direct digital RF amplitude modulator

This paper describes a direct digital RF amplitude modulator, which uses a 10-bit linear interpolation current steering digital to analog converter (DAC) and a Gilbert cell mixer to generate an RF amplitude modulated signal directly. The linear interpolation increases the attenuation of the DACs image components. The low pass filter (LPF) is eliminated, and the RF transmitter structure can be simplified. This modulator is suitable for realizing the system-on-chip design. The chip has been fabricated in a 0.35 /spl mu/m, 3.3 V digital CMOS process.

A non-feedback multiphase clock generator

This paper introduces the design of a new multiphase clock generator with no feedback loop. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit has been fabricated in a standard 0.35 /spl mu/m, 3.3 V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1.5 GHz.