Jiri Kadlec

Arithmetic on the European logarithmic microprocessor

A new European research project aims to develop a microprocessor based on the logarithmic number system, in which a real number is represented as a fixed-point logarithm. Multiplication and division therefore proceed in minimal time with no rounding error. However, the system can only offer an overall advantage over floating-point if addition and subtraction can be performed with speed and accuracy at least equal to that of floating-point, but these operations require the interpolation of a nonlinear function which has hitherto been either time-consuming or inaccurate. We present a procedure by which additions and subtractions can be performed rapidly and accurately and show that these operations are thereby competitive with their floating-point equivalents. We then present some large-scale case studies which show that the average performance of the LNS exceeds floating-point, in terms of both speed and accuracy.

The Gauss-Seidel fast affine projection algorithm

In this paper we propose a new stable fast affine projection algorithm based on Gauss-Seidel iterations (GSFAP). We investigate its implementation using the logarithmic number system (LNS) and compare it with two other fast affine projection (FAP) algorithms. Simplified and multi-input GSFAP versions are also proposed. We show that the algorithm is only marginally more complex than NLMS and simpler than other FAP algorithms. Its application for acoustic echo cancellation is also investigated.

Logarithmic Number System and Floating-Point Arithmetics on FPGA

An introduction to a logarithmic number system (LNS) is presented. Range and precision of this arithmetic is briefly discussed. We show that the LNS arithmetic is suitable for a FPGA implementation. A case study will compare parameters of our LNS arithmetic library to a conventional floating-point arithmetic.

The European Logarithmic Microprocesor

In 2000 we described a proposal for a logarithmic arithmetic unit, which we suggested would offer a faster, more accurate alternative to floating-point procedures. Would it in fact do so, and could it feasibly be integrated into a microprocessor so that the intended benefits might be realized? Here, we describe the European logarithmic microprocessor, a device designed around that unit, and compare its performance with that of a commercial superscalar pipelined floating-point processor. We conclude that the experiment has been successful, and that for 32-bit work, logarithmic arithmetic may now be the technique of choice.

Increasing the level of abstraction in FPGA-based designs

Traditional design techniques for FPGAs are based on using hardware description languages, with functional and post-place-and-route simulation as a means to check design correctness and remove detected errors. With large complexity of things to be designed it is necessary to introduce new design approaches that will increase the level of abstraction while maintaining the necessary efficiency of a computation performed in hardware that we are used to today. This paper presents one such methodology that builds upon existing research in multithreading, object composability and encapsulation, partial runtime reconfiguration, and self adaptation. The methodology is based on currently available FPGA design tools. The efficiency of the methodology is evaluated on basic vector and matrix operations.

Accelerating Microblaze Floating Point Operations

The MicroBlaze processor serves in many FPGA designs as the central 32 bit CPU with access to the global off chip memory and peripherals. MicroBlaze provides FSL links for up to 8 coprocessors. We present two MicroBlaze designs. The first design works with 8 PicoBlaze-based accelerators for pipelined, single-precision floating point vector-oriented operations, and delivers over 1.2 GFLOPs. The second design uses 4 similar double precision accelerators and delivers 600 MFLOPs. The acceleration results are documented on batch computation of a finite impulse response filter. Each PicoBlaze soft core can be re-programmed by MicroBlaze. This provides a framework for a partial dynamic change of the functionality of accelerators. This program change can be done via the FSL link in parallel with the current computation of the accelerator.

The European Logarithmic Microprocessor - a QR RLS application

In contrast to all other microprocessors, which use floating-point for their real arithmetic, the European Logarithmic Microprocessor is the worlds first device to use the logarithmic number system for this purpose. Simulation work has already suggested that this can deliver approximately twofold improvements in speed and accuracy. This paper describes the ELM device, and illustrates its operation using an example from a class of RLS algorithms.

Implementation of (Normalised) RLS Lattice on Virtex

We present an implementation of a complete RLS Lattice and Normalised RLS Lattice cores for Virtex. The cores accept 24-bit fixed point inputs and produce 24-bit fixed point prediction error. Internally, the computations are based on 32bit logarithmic arithmetic. On Virtex XCV2000E- 6, it takes 22% and 27% of slices respectively and performs at 45 MHz. The cores outperform (4-5 times) the standard DSP solution based on 32 bit floating point TMS320C3x/4x 50MHz processors

Pipelined implementations of the a Priori Error-Feedback LSL algorithm using logarithmic arithmetic

In this paper we present several implementations of the Modified A Priori Error-Feedback LSL (EF-LSL) algorithm [1] on the VIRTEX FPGA. Its computational parallelism and pipelinabilty are important advantages. Internally, the computations are based on the logarithmic number system. We compare 32-bit (SINGLE-ALU or DUAL-ALU version) and 20-bit (QUADRI-ALU versions). We show that the LNS implementation can outperform the standard DSP solutions based on 32-bit floating-point processors.

Paper: The block regularised parameter estimator and its parallelisation

Kulhavys regularised parameter identification concept protects the adaptive recursive estimation of a linear regression model from numerical difficulties associated with standard exponential weighting in cases where the processed data is not sufficiently exciting. Unfortunately, such robustness incurs a severe penalty in computational complexity, which militates against practical applications. This paper presents a new block regularised parameter estimator that is compatible with the requirements for implementation on a parallel architecture. Owing to the accumulated regularisation in blocks, the achieved throughput of the estimator is an order of magnitude higher in comparison with the general framework of Kulhavy and more comparable to recursive least squares on a systolic array. The processing cells operate at almost 100% efficiency, and are only connected to their nearest neighbours by one-directional connections. This new parameter estimator offers significant potential for identification, adaptive filtering and adaptive control applications, particularly in the real-time domain.