Jizhong Zhao

Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache

Due to its great scalability, fast read access, low leakage power, and nonvolatility, magnetic random access memory (MRAM) appears to be a promising memory technology for on-chip cache memory in microprocessors. However, the write-to-MRAM process is relatively slow and results in high dynamic power consumption. Such inherent disadvantages of MRAM make researchers easily conclude that MRAM can only be used for low-level caches (e.g., L2 or L3 cache), where cache memories are less frequently accessed and slow write to MRAM can be more easily compensated using simple architectural techniques. By developing a hybrid cache architecture, this paper attempts to show that, with appropriate architecture design, MRAM can also be used in L1 cache to improve both the energy efficiency and soft error immunity. The basic idea is to supplement the MRAM L1 cache with several small SRAM buffers, which can substantially mitigate the performance degradation and dynamic energy overhead induced by MRAM write operations. Moreover, the proposed hybrid cache architecture is also an efficient solution to protect cache memory from radiation-induced soft errors, as MRAM is inherently invulnerable to emissive particles. Simulation results show that, with only less than 2% performance degradation, the proposed design approach can reduce the power consumption by up to 76.1% on average compared with the traditional SRAM L1 cache. In addition, the architectural vulnerability factor of L1 data cache is reduced from 28.3% to as low as 0.5%.

Haze Removal Using the Difference- Structure-Preservation Prior

Fog cover is generally present in outdoor scenes, which limits the potential for efficient information extraction from images. In this paper, the goal of the developed algorithm is to obtain an optimal transmission map as well as to remove hazes from a single input image. To solve the problem, we meticulously analyze the optical model and recast the initial transmission map under an additional boundary prior. For better preservation of the results, the difference-structure-preservation dictionary could be learned, such that the local consistency features of the transmission map could be well preserved after coefficient shrinkage. Experimental results show that the method preserves the natural appearance of the image.

Hardware Implementation of Reconfigurable 1D Convolution

Convolution has been extensively used in image processing and computer vision, including image enhancement, smoothing, and structure extraction. However, convolution operation typically requires a significant amount of computing resources. A novel one-dimensional (1D) convolution processor with reconfigurable architecture is implemented in this study. This processor is a combination of a line buffer, controller units, as well as a reconfigurable and separable convolution module. The use of a reconfigurable architecture and separable convolution approach improves the flexibility and performance of the convolution processor. The reconfigurable and separable convolution array, which is the main component of the processor, can simultaneously execute convolution operation with different kernels, with a maximum kernel size of up to 24 × 24. Experimental results show that the maximum frames rate of the processor is approximately 194 frames per second (fps), which exceeds the real-time requirement. Synthesis results show that the processor occupies 13.39 mm 2 at a 204 MHz system clock and consumes a power of 419 mW at maximum kernel size at a 120 MHz system clock in SMIC 0.18 μm CMOS technology. Verification experiments on field programmable gate arrays (FPGAs) demonstrate that the processor is suitable for real-time image processing applications even for high-resolution images.

Hardware Implementation for Real-Time Haze Removal

Haze removal is useful in computational photography and computer vision applications. Although many haze removal algorithms have been proposed, their computational efficiency requires improvement. A real-time haze removal method is presented in this paper. The method is based on the concept of a dark channel prior. To enhance the haze removal performance, an approximate method to estimate the atmospheric light and transmission is employed. For embedded system applications, a hardware architecture to perform real-time haze removal is proposed. The hardware can achieve 116 MHz on Stratix FPGA. The simulation results indicate that the hardware is highly efficient and performs well. It obtains good image recovery results and satisfies the real-time requirement even for large images.

Hierarchical and Parallel Pipelined Heterogeneous SoC for Embedded Vision Processing

Object recognition is widely used in vision computing for various applications. Traditional CPU and application specific integrated circuit for vision computing cannot provide high performance and enough flexibility, which limit the use of vision systems. In this paper, a hierarchical and parallel pipelined heterogeneous chip for object recognition is proposed to achieve high flexibility, high performance, and area efficiency. In addition, a reformulation of 3D position estimation is proposed. The method uses single precision to achieve the short computing time and accuracy requirement. The hardware resource is small. Application-specific components, such as connected component information extractor and information extraction accelerator, are designed for high performance. Reconfiguration processors and application-specific instruction set processor are introduced to improve flexibility. These components are connected to hierarchical parallel buses. The chip is fabricated in 180-nm CMOS technology and occupies 72.25 mm2 with 1.09M bits on-chip memory. It delivers 204 GOPS + 665M FLOPS operations. The results show that this hierarchical and parallel pipelined heterogeneous chip is suitable for embedded vision systems.

RFIPad: Enabling Cost-Efficient and Device-Free In-air Handwriting Using Passive Tags

An important function of smart environments is the ubiquitous access of computing devices. In public areas such as hospitals, libraries, and airports, people may want to interact with nearby computing systems to get information, such as directions to a hospital room, locations of books, and flight departure/arrival information. Touch screen based displays and kiosks, which are commonly used today, may incur extra hardware cost or even possible germ and bacteria infection. This work provides a new solution: users can make queries and inputs by performing in-air handwriting to an array of passive RFID tags, named RFIPad. This input method does not require human hands to carry any device and hence is convenient for applications in public areas. Besides the mobile and contactless property, this system is a cost-efficient extension to current RFID systems: an existing reader can monitor multiple RFIPads while performing its regular applications such as identification and tracking. We implement a prototype of RFIPad using commercial off-the-shelf UHF RFID devices. Experimental results show that RFIPad achieves >91% accuracy in recognizing basic touch-screen operations and English letters.

Effective haze removal under mixed domain and retract neighborhood

Abstract The quality of images would exhibit degraded visibility during inclement weather conditions. We proposed a novel method for estimating an optimal transmission map and recovering the real scene. Under HSI color model, saturation layer and intensity layer are mixed together for obtaining the rough transmission. To avoid halos and artifacts, proposed approach employs edge preserving constraint of shrinkage neighborhood on the color line model, which can maintain maximum smoothness and sharp edges in the refined transmission map. A comparative experiment with a few previous methods shows improvement visual results.

Elementary Function Computing Method for Floating-Point Unit

CORDIC is a simple algorithm that uses adders and shifters to compute elementary functions. CORDIC has wide applications because of its low resource consumption and simple hardware architecture. CORDIC traditionally dedicates calculation units only for integer or fixed-point number. Control scheme and structure are also complicated. In this paper, we propose a floating-point elementary function computing method combined with dedicated circuits and floating-point arithmetic components. The arithmetic components minimize hardware resource and enhance flexibility. Dedicated circuits improve computing speed and simplify hardware structure. The floating-point elementary function processor can be easily designed using the method described. And FPU can be modified to have the capability of elementary function computing. A double precision floating-point elementary function processor with a simple and flexible structure is designed. A single precision processor is implemented with an FPGA and synthesized with Synopsys Design Compiler. Synthesis and experimental results show that the processor can calculate all the common elementary functions. The processor has merits of simple structure and design, flexibility, and wide application range.

SALM: Smartphone-Based Identity Authentication Using Lip Motion Characteristics

With rapid development and popularity, smartphones have been of importance in our daily life. Despite of its convenience in communication and computing, smartphones also lead potential security threats to users. Existing methods on smartphones for protecting users privacy mainly depend on password or fingerprint based authentication. Most smartphone passwords are very simple and easy to guess or crack, and fingerprinting requires extra hardware and hence increases the price of smartphones. In this paper, we present a smartphone-based identity authentication method based on users lip motion characteristics, called SALM, which can be used as an additional authentication with password. SALM extracts the feature of lip movements as the authentication token, which is unique for each user. We implement SALM using off-the-shelf smartphones and evaluate its performance via extensive experiments. The results show that the overall accuracy of user authentication using SALM (without password) is higher than 96%.

Matrix computing coprocessor for an embedded system

Matrix computing based on software, particularly floating point matrix computing, is slow and often becomes a problem in overall embedded systems. A matrix computing coprocessor (MCC) is developed in this study to improve the performance of matrix computing. The proposed MCC, which is an application-specific instruction set processor for the construction of a high-performance embedded system, can independently implement the entire algorithm, including floating point matrix computing. A good definition matrix operation instruction set is also presented. A single floating-point MCC and an embedded system with the MCC are implemented. Experimental results show that the proposed MCC exhibits high performance and has excellent flexibility and good application prospect.