Jochen Kraft

Through Silicon Via Reliability

Vertical integration of diverse semiconductor technologies can be achieved by utilizing interconnections through entire silicon substrates, known as through silicon vias (TSVs). TSVs present an interesting case study for reliability evaluation, given the particular fabrication technologies, geometries, and potential failure modes associated with such structures. A specific TSV technology is introduced, and key parameters for reliability assessment, such as residual stress, resistance, leakage, and dielectric breakdown, are discussed. Reliability data are presented, including the characterization of TSV parameters as a function of various accelerated lifetime stress tests, as well as assessments of the density and impact of TSV manufacturing defects. The presented data demonstrate that while the TSV is inherently quite robust, latent manufacturing defects pose a significant risk to long-term reliability. Screening methodologies, defect modes, failure analysis methods, process improvement, and correspondingly improved defect density results are discussed. The results are considered pertinent to the development and reliability of novel 3-D integrated process technologies.

Optimized integrated micro-hotplates in CMOS technology

Within this work the development of integrated Micro-HotPlates (μHPs) for gas sensing applications as a System-On Chip (SOC) is presented. As gas sensors exploit resistance variations of sensing materials like SnO₂ at high operating temperatures, integrated μHPs are required for the dynamic and low power operation of these sensors. The optimized μHP structures consist of fully released membranes with polysilicon heaters in the oxide stack and suspension arms to the bulk silicon. Thanks to the optimized μHP design very low power consumption of P_el ~20mW at high temperatures up to T=400°C together with a thermal uniformity of only ΔT~1K across the active area ending up in the highest reported efficiency of =26-20K/mW for standard CMOS hotplates is achieved. Further a rise/fall time t_rise/t_fall =4.5/5.4ms was measured. Long term stability of the μHP has been proven applying ten million measurement cycles. Thermography confirmed the temperature distribution and functionality. The realized hotplates cover a heating area of A_μHP=100×100μm²/70×70μm² at arm lengths of l_arm=70μm/50μm respectively. The chips have been realized in 0.35μm standard CMOS technology and released in a post process MEMS-etching step.

Passivation integrity investigations for through wafer interconnects

Through wafer interconnects (TWI) with diameters greater than 50 mum have the advantage of extremely low contact resistances. The mechanics of the layers inside the TWI has to be well understood order to avoid passivation cracks. Results of simulation and mechanical investigations are discussed in this paper.

Usage of HBTs beyond BV/sub CEO/

Heterojunction bipolar transistors (HBTs) are preferred devices for designers to realise power amplifiers due to their good noise and HF performance. The collector emitter breakdown with open base (BV/sub CEO/) is in first order limiting the HBT operation conditions, especially for high output power where it is useful to utilise the complete voltage swing. In real applications with an ohmic connection of the base to a voltage source the breakdown condition can be released. We deliver a new formula for the emitter collector breakdown BV/sub CER/ as a function of the external base resistor, the emitter base voltage and the temperature. A safe operating area (SOA) is defined enabling the reliable usage of HBTs for emitter collector voltages higher than BV/sub CEO/ depending on base emitter voltage range and temperatures.

Through Silicon Via (TSV) defect investigations using lateral emission microscopy

Abstract Infra-red photoemission microscopy has been applied for the localization of defects in 3D integrated circuits containing Through Silicon Vias (TSVs). For these investigations, the familiar (planar) emission microscopy configuration was extended to allow imaging and emission microscopy on vertical TSV sidewalls, from versatile 3D viewpoints. Flexible viewing orientation was achieved by introducing an additional reflecting surface into the optical path. Precise alignment of the angle of incidence at the air–silicon interface, with sufficient accuracy to ensure no problematic refraction-related errors, was possible using this experimental set-up. Three examples are presented, showing defect localizations and underlying physical leakage mechanisms in TSV structures.

X-ray nanodiffraction analysis of stress oscillations in a W thin film on through-silicon via

X-ray nanodiffraction is used to evaluate axial and tangential residual stress distributions in a W thin film deposited on the scalloped inner wall of a through-silicon via. The results reveal oscillatory stress distributions which correlate well with the scallop wavelength and morphology.

Modeling the Growth of Tin Dioxide Using Spray Pyrolysis Deposition for Gas Sensor Applications

In order for the gas sensor devices to enjoy the miniaturization trend that has consumed much of the electronic device industry, major research in the field is undertaken. The bulky sensor devices of previous generations can not easily be incorporated into a CMOS processing sequence, because of their bulky nature and potential higher cost of production. More recently, materials such as zinc oxide and tin dioxide have shown powerful gas sensing capabilities. Among many potential deposition methods, spray pyrolysis has become a popular approach because of its ease of use and cost effectiveness. A model for spray pyrolysis deposition is developed and implemented within the level set framework. The implementation allows for a smooth integration of multiple processing steps for the manufacture of smart gas sensor devices. From the observations, it was noted that spray pyrolysis deposition, when performed with a gas pressure nozzle, results in good step coverage, analogous to a CVD process. This is mainly due to the atomizing nozzle being placed at a reasonable distance away from the wafer surface and reducing the droplets volume and mass in order to ensure they fully evaporate prior to contact with the substrate surface. A topography simulator for this deposition methodology is presented.

Photonic–Electronic Integration With Bonding

By co-integrating optics and electronics on the same chip, high-functionality, high-performance and highly integrated devices can be fabricated with a well-mastered microelectronics fabrication process. Different integration schemes with bonding are presented either with die-to-wafer or wafer to wafer bonding. Depending of the applications and the maturity level of the technologies, the strategies for integration will differ.

BV CER - Increased Operating Voltage for SiGe HBTs

SiGe-heterojunction bipolar transistors (HBTs) still sustain their leading RF-application position due to their good noise and HF properties. They also offer a relatively high operating voltage, which is limited by BVCEO, the emitter collector breakdown voltage with open base. We show that BVCER, the avalanche breakdown with a resistor RB connected to the base, can be used to define reliable operating conditions exceeding BVCEO. The measured BVCER data correlate very well with values calculated from basic transistor parameters and their corresponding multiplication factor data. The functionality of this concept is verified by investigating a power amplifier circuit used at emitter collector voltages exceeding BV CEO in operational mode enabling significant higher output power

Integration of Photonic Detectors in Standard SiGe HBT BiCMOS

For certain purposes SiGe-BiCMOS technology has become an accepted alternative to III/V based technologies. Potential applications can so far be found in the analog, RFand mixed signal market segments, which exploit the high transit frequencies and low-noise features offered by this technology. In the past years optical data communication and optical storage applications have triggered the monolithic integration of photodetectors (PD) in photodiode integrated circuits (PDICS). This has become necessary for technical reasons to obtain increased bandwidths due to the elimination of parasitic capacitances arising from the external wiring between PD and IC. And it was also a cost-driven process. The opportunity to place many parallel optical receivers on one chip might open the door to optical interconnects. Apart from classical optical communication applications using wavelengths in the near IR at 850nm and IR at 1.3-1.5μm, optical data storage applications like CD and DVD have proven to be very successful at 780nm and 650nm, respectively. The next technology of optical mass storage media has already been introduced by Toshiba (HDDVD) and will soon be followed by the blu-ray disc. Both technologies use blue light at 410nm and are extremely cost driven because they are intended for the mass market. In this paper we try to point out the advantages of a SiGe:C-BiCMOS process platform for the implementation of multi-wavelength sensitive photodetector devices. A schematic cross section through a PD implemented in austriamicrosystems 0.35 SiGe-process (1) is shown in Figure 1. The device consists of two vertically arranged pn-junctions formed by a SiGe:C-anode and a n-tub cathode, resp., an n+-buried layer(BL)-cathode versus the substrate anode. The conversion of short-wavelength light at 410nm is done by the SiGe:C-PD and turned out to be very efficient and extremely fast (2). This high performance with respect to bandwidth can be attributed to the abruptness of the junction obtained by epitaxial and in-situ doped growth of the SiGe-anode layer, the implementation of carbon hindering out diffusion of boron and allowing a higher Ge concentration. The graded Ge concentration results in a quasi-electric field in the conduction band accelerating photogenerated minority carriers (electrons) out of the highly doped anode making recombination more unlikely and therefore increasing both speed and responsivity. The second junction is used to harvest light of longer wavelengths (660nm and 785nm) and to make this device favorable for CD/DVD and HDDVD resp. blu-ray applications. The advantage of the chosen double photodiode(DPD) concept of two vertically arranged pn-junctions over other approaches like pin photodiodes (3) is the easy and straightforward process integration. No further process steps or mask levels are necessary inhibiting thus further process complexity and extensive requalification measures. The higher process complexity of a SiGe:C–BiCMOS process technology with respect to a bare CMOS technology turns out to be an advantage at a closer look. In fact it offers more flexibility to cope with problems that arise in conjunction with the integration of PDs. E.g. to overcome the poor optical quantum efficiency that results from mismatched refraction indices of silicon resp. SiGe and the “backend”-materials silicon dioxide and the nitride passivation. Here a silicon dioxide/silicon nitride stack that is originally used as etch stop for structuring the emitter poly within the SiGe:C-BiCMOS process turns out to be also a very effective antireflective coating. It significantly increases the optical quantum efficiency from 50-75% to 75%-90%. High responsivities in the blue spectral range might be interesting not only for blu-ray disc double-layer storage media with reduced reflected light intensity, but generally for applications with low light intensity. The specific setup of our SiGe:C photodiode offers an additional feature we attribute to avalanche multiplication. At sufficiently high reverse bias (> 5V) the PD’s n-tub cathode (Figure 1) turns out to be fully depleted resulting in a very high responsivity of up to 0.6 A/W. The high bias could be generated on chip (4) by the implementation of a voltage up converter. A further example how the alleged higher SiGe:C-BiCMOS process complexity can be beneficially used to enhance diode performance will be presented in conjunction with the reduction of dark currents. Originally we measured dark currents up to 0.8% of the photocurrent at 10V reverse bias. With the help of a p+-implant from the CMOS process module, we managed to drastically reduce leakage currents.