Joerg Vollrath

DDR2 DRAM output timing optimization

The speed of DRAMs is increasing from generation to generation. This paper gives an overview of typical DRAM output timing challenges. Tight output timing specifications in the order of several 100ps are presented. Specification requirements lead to efforts to improve the output driver design. A systematic test strategy evaluates limits of automatic test equipment (ATE) overall timing accuracy (OTA) and device performance. Systematic output timing characterization data leads to guidelines for design improvements. A good characterization strategy gives a feedback to the design of specific weaknesses of output drivers and enables ATEs to test these parameters with high accuracy

Efficient DRAM Characterization Using Improved Searches, Branching and Automated Pattern Generation

Characterization provides electrical values for all parameters of the data sheet. Modern DRAMs have increasing numbers of operation modes resulting in ever larger numbers of characterization test items and larger numbers of test patterns. Test time is not only determined by the number of test items, but also by the search algorithm. Binary search can speed up single device measurements, but is difficult to implement for multiple device measurements. A new multiple parameter search strategy presented here can reduce characterization test time and allows diagnosis. A branching strategy to identify performance limiting single test items is presented. Automatic pattern generation for different operation modes and some timing searches are explained. This can speed up development time and optimize test time.