Johan Löfgren

Area-Efficient Configurable High-Throughput Signal Detector Supporting Multiple MIMO Modes

This paper presents a low-complexity, high-throughput, and configurable multiple-input multiple-output (MIMO) signal detector design solution targeting the emerging Long-Term-Evolution-Advanced (LTE-A) downlink. The detector supports signal detection of multiple MIMO modes, which are spatial-multiplexing (SM), spatial-diversity (SD), and space-division-multiple-access (SDMA). Area-efficiency is achieved by algorithm and architecture co-design where low-complexity, near-maximum-likelihood (ML) detection algorithms are proposed for these three MIMO modes respectively while keeping in mind that the operations can be reused among different modes. A parallel multistage VLSI architecture is accordingly developed that achieves high detection throughput and run-time reconfigurability. To further improve the implementation efficiency, the detector also adopts an orthogonal-real-value-decomposition (ORVD) aided candidate-sharing technology for low-cost partial Euclidean distance calculation and a distributed interference cancelation scheme for a critical path delay reduction. The proposed multi-mode MIMO detector has been designed using a 65-nm CMOS technology with a core area of 0.25 mm2 (the equivalent gate-count is 88.2 K), representing a 22% less hardware-resource use than the state of art in the open literature. Operating at 1.2-V supply with 165-MHz clock, the detector achieves a 1.98 Gb/s throughput when configured to the 4 × 4 64-QAM spatial-multiplexing mode. The corresponding normalized energy consumption is 51.8 pJ per bit detection.

Channel estimation for a mobile terminal in a multi-standard environment (LTE and DVB-H)

In this paper, we present an analysis of different channel estimator structures that can be used and efficiently implemented with minor configuration changes of a common hardware for both LTE and DVB-H. Such common estimator structures for LTE and DVB-H allow algorithm and hardware reuse when both standards are implemented on the same platform. In this approach, a core estimator will be utilized to address parameter estimation for the two standards. The estimators exploit similarities in pilot patterns between LTE and DVB-H. The estimation techniques are discussed taking both algorithm and complexity issues into account.

Low-Complexity Likelihood Information Generation for Spatial-Multiplexing MIMO Signal Detection

Signal detection algorithms providing likelihood information for coded spatial-multiplexing multiple-input-multiple-output (MIMO) wireless communication systems pose a critical design challenge due to their prohibitively high computational complexity. In this paper, we present a low-complexity soft-output detection algorithm by adopting four implementation-friendly algorithm-level improvements to the fixed-complexity sphere decoder. More specifically, we introduce a reliability-dependent tree expansion approach and an on-demand list-size reduction scheme for low-cost candidate list generation. In terms of performance improvement, we apply an early bit-flipping strategy and utilize the l1-norm distance representation. The algorithm is evaluated by computer simulations performed over Rayleigh flat fading channels and computational complexity analysis. Compared with the soft-output K-Best algorithm, the proposed algorithm saves at least 60% of the computations for detecting 4 × 4 64-quadrature amplitude modulation (QAM) MIMO signal and, at the same time, provides better detection performance, making it a promising detection scheme for real-life hardware implementation.

On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems

This paper treats the hardware architecture and implementation of mixed radix FFTs with cores of radix 3 and radix 5 in addition to the standard radix 2 core. The implementation flow graphs of the higher radix cores are presented together with a description of how these cores affect a pipelined FFT implementation. It is shown that the mixed radix FFT is more expensive than the radix 2 implementation - a mixed radix FFT of 1200 points require 36 real multipliers in a pipelined implementation whereas a 2048 radix 2 FFT needs 30 real multipliers. However, half of the multipliers in the mixed radix case can be constant. Therefore it is still feasible to use the mixed radix FFT if an algorithm calls for it.

A sign-bit auto-correlation architecture for fractional frequency offset estimation in OFDM

This paper presents an architecture of an autocorrelator for Orthogonal Frequency Division Multiplexing systems. The received signal is quantized to only the sign-bit, which dramatically simplifies the frequency offset estimation. Hardware cost is reduced under the assumption that synchronization during acquisition does not have to be very accurate, but sufficient for coarse estimation. The architecture is synthesized towards a 65nm low-leakage high threshold standard cell CMOS library. The proposed architecture results in area reduction of 93% if compared to typical 8-bit implementation. The area occupied by the architecture is 0.063 mm2. The architecture is evaluated for WLAN, LTE and DVB-H. Power simulations for DVB-H transmission shows a power consumption of 4.8µW per symbol.

Improved Matching-Pursuit Implementation for LTE Channel Estimation

An implementation of a reduced complexity matching pursuit channel estimator for LTE is presented. The design contains an FFT/IFFT module with non-radix-2 units and a core estimator. The module is flexible enough to perform FFT and IFFT at different resolutions needed, using the same hardware. Based on prior work the needed internal word lengths are found. Internal shifts are employed to maximize the use of available resources. The design is implemented in a 65 nm low power process from STMicroelectronics. The total area of the implementation is 1 mm2 design, including input pads and extra control logic. The algorithmic improvements reduce the complexity by up to 56% compared to prior art. At the same time estimator shows great improvement in speed, allowing over 6 times the number of estimations in the same time. Power consumption of the estimator is simulated to ~ 20 mW, running at 70 MHz.

VLSI Implementation of a Soft-Output Signal Detector for Multimode Adaptive Multiple-Input Multiple-Output Systems

This paper presents a multimode soft-output multiple-input multiple-output (MIMO) signal detector that is efficient in hardware cost and energy consumption. The detector is capable of dealing with spatial-multiplexing (SM), space-division-multiple-access (SDMA), and spatial-diversity (SD) signals of 4 × 4 antenna and 64-QAM modulation. Implementation-friendly algorithms, which reuse most of the mathematical operations in these three MIMO modes, are proposed to provide accurate soft detection information, i.e., log-likelihood ratio, with much reduced complexity. A unified reconfigurable VLSI architecture has been developed to eliminate the implementation of multiple detector modules. In addition, several block level technologies, such as parallel metric update and fast bit-flipping, are adopted to enable a more efficient design. To evaluate the proposed techniques, we implemented the triple-mode MIMO detector in a 65-nm CMOS technology. The core area is 0.25 mm2 with 83.7 K gates. The maximum detecting throughput is 1 Gb/s at 167-MHz clock frequency and 1.2-V supply, which archives the data rate envisioned by the emerging long-term evolution advanced standard. Under frequency-selective channels, the detector consumes 59.3-, 10.5-, and 169.6-pJ energy per bit detection in SM, SD, and SDMA modes, respectively.

Hardware implementation of an SVD based MIMO OFDM channel estimator

This paper presents a hardware design of an SVD based channel estimator. The details of the design are explained and some key aspects are discussed. The design has been implemented and tested on an FPGA and synthesized for an ASIC in 130 nm technology. It is shown that it is possible to get a clock frequency of 179 MHz for a 1.38 mm2 design. This corresponds to ~30 M estimates per second, which is more than needed in current wireless systems. Further, simulations show that this design would consume an average power of around 8.5 mW with a peak power at 14.2 mW. The presented data shows that it is possible to use these kind of advanced channel estimation strategies in wireless receivers, even though there has been no prior reports of these being implemented.

Improved matching pursuit algorithm and architecture for LTE Channel Estimation

This paper describes a novel approach to a Matched Pursuit LTE Channel Estimator. It is shown that the total complexity of the estimator can be reduced by, perhaps counter-intuitively, increasing the resolution of the estimator, since for certain choices of resolution a number of multiplication factors will be zero. An architecture is presented that implements the novel algorithm. By increasing the resolution from 2048 to 2400 points it is shown that the number of multiplications in the core unit is reduced by −40 % and the total complexity of the estimator by more than 10 %. The RAM memory needed increase by −17 % since more values need to be stored, but the lookup table is reduced by −71 %.

Hardware architecture of an SVD based MIMO OFDM channel estimator

This paper presents an architecture of an SVD based channel estimator. A number of simplifications of the estimator are presented. These simplifications reduces the complexity of the estimator enough to allow for a hardware implementation. A system is defined, in which the channel estimator is to be used. It is shown that with the proposed pilot symbol pattern and the usage of the channel correlation properties the estimator will reduce the number of multipications with 66 % compared to a brute force attempt. The hardware architecture of the channel estimator is also described. The estimator will have a throughput of 1/6th of the achievable clock speed and the word lengths are chosen such that there will be only a negligible increase in mean square error compared to the floating point case and still a 5 time improvement compared to the least square estimator.