Johann Pfeiffer

RAM memory circuit having a plurality of banks and an auxiliary device for testing

Method and auxiliary device for testing a RAM memory circuit

Memory having internal column counter for compression test mode

RAM memory circuit and method for memory operation at a multiplied data rate

Circuit and method for writing and reading data from a dynamic memory circuit

Memory circuit having a plurality of memory areas

Semiconductor memory and method for operating the semiconductor memory

Integrated circuit having a voltage monitoring circuit and a method for monitoring an internal burn-in voltage

Semiconductor memory with address decoding unit, and address loading method

Semi-conductor component with clock relaying device