John A. McNeill

Split ADC architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC

For original article by J. McNeill et al. see ibid., vol.40, no.12, p.2437-45, Dec. 2005.

Jitter in ring oscillators

This paper describes a theoretical framework for analyzing and predicting jitter in ring oscillators. These oscillators are becoming more popular in low jitter applications, but the mechanisms underlying their jitter performance have been poorly understood. A comparison with analysis techniques for harmonic and relaxation oscillators shows that a different approach is needed to design for low jitter in rings. The approach taken is in the time domain, considering each delay stage to add a uniform amount of phase in a varying an amount of time. The theory is applied to experimental results from ring oscillators of several different lengths.<<ETX>>

All-Digital Background Calibration of a Successive Approximation ADC Using the “Split ADC” Architecture

The “split ADC” architecture enables fully digital calibration and correction of nonlinearity errors due to capacitor mismatch in a successive approximation (SAR) ADC. The die area of a single ADC design is split into two independent halves, each converting the same input signal. Total area and power is unchanged, resulting in minimal increase in analog complexity. For each conversion, the half-sized ADCs generate two independent outputs which are digitally corrected using estimates of capacitor mismatch errors for each ADC. The ADC outputs are averaged to produce the ADC output code. The difference of the two outputs is used in a background calibration algorithm which estimates the error in the correction parameters. Any nonzero difference drives an LMS feedback loop toward zero difference which can only occur when the average error in each correction parameter is zero. A novel segmentation and shuffling scheme in the SAR capacitive DAC enables background calibration for a wide range of input signals including dc. Simulation of a 16 bit 1 Msps SAR ADC in 180 nm CMOS shows calibration convergence within 200 000 samples.

“Split ADC” Calibration for All-Digital Correction of Time-Interleaved ADC Errors

The ldquosplit analog-to-digital converter (ADC)rdquo architecture enables fully digital calibration and correction of offset, gain, and aperture-delay mismatch errors in time-interleaved ADCs. The calibration of M interleaved ADCs requires 2M + 1 half-sized ADCs, a minimal increase in analog complexity. Each conversion is performed by a pair of half-sized ADCs, generating two independent outputs that are digitally corrected using estimates of offset, gain, and aperture-delay errors. The ADC outputs are averaged to produce the ADC output code. The difference of the outputs is used in a calibration algorithm that estimates the error in the correction parameters. Any nonzero difference drives a least-mean-square feedback loop toward zero difference, which can only occur when the average error in each correction parameter is zero. A simulation of a 4 : 1-time-interleaved 16-bit 12-MSps successive-approximation-register ADC shows calibration convergence within 400 000 samples.

Digital Background-Calibration Algorithm for “Split ADC” Architecture

The ldquosplit ADCrdquo architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms.

Jitter in oscillators with 1/f noise sources

A higher 1/f noise corner is introduced in the latest deep sub-micron process. Hence the characterization of jitter due to the 1/f noise becomes crucial for practical applications. This work presents a simple model to relate the time domain jitter and frequency domain phase noise in the presence of 1/f noise sources, and reveals the relationship between the 1/f transition time and the 1/f/sup 3/ phase noise corner. The measured results from ring oscillators fabricated in a 0.18/spl mu/process show that the error of this simple model is within 10%.

Single-ended to differential converter for multiple-stage single-ended ring oscillators

This paper presents an improved technique for single-ended to differential conversion that allows for the use of single-ended CMOS ring oscillators in an otherwise fully differential integrated circuit environment. An interpolating resistor network is used to derive a fully differential representation of the single-ended voltage-controlled-oscillator (VCO) signal. The technique preserves the fundamental noise performance of single-ended ring oscillators in the presence of supply and substrate interference. Experimental results in a 0.35-/spl mu/m CMOS process show the applicability of this technique at the VCO speeds of up to 1.3 GHz.

A 150 mW, 155 MHz phase locked loop with low jitter VCO

This paper describes a 155 MHz clock recovery phase locked loop (PLL) for use in fiber optic serial data communication systems. The PLL incorporates a low jitter voltage controlled ring oscillator. Some of the inherent limitations of the ring architecture, as well as design techniques for dealing with those limitations, are discussed. The PLL chip has been fabricated in a dielectrically isolated complementary bipolar process, occupies a die area of 2 mm/spl times/3 mm, and consumes 150 mW operating from a 5V supply.<<ETX>>

A digital-PLL-based true random number generator

A true random number generator (RNG) based on a digital phase-locked loop (PLL) has been designed and implemented in a 1.5/spl mu/m CMOS process. It achieved an output data rate of 100 kbps from the sampling of two 30MHz ring oscillators, and successfully passed the NIST test suite SP800-22.

A simple method for relating time- and frequency-domain measures of oscillator performance

This paper presents a simple technique for linking time domain (jitter) and frequency domain (phase noise) measures of oscillator performance. The key concept is the definition of a single figure-of-merit in the time- or frequency-domain that relates system-level performance (such as jitter or phase noise) to circuit-level parameters (such as power dissipation and signal amplitude). This technique is particularly applicable to circuit- and system-level design of voltage-controlled oscillators (VCOs) and phase-locked loops (PLLs). The technique allows VCO and PLL design and characterization to take place in the domain (time or frequency, PLL open-loop or closed-loop) that provides the most insight into sources of jitter, while allowing a direct link to system-level performance as measured in any other domain. The methodology also speeds simulation since only the open loop VCO need be simulated, which allows a substantial savings in simulation time. Design examples and experimental results are presented for existing PLLs showing good agreement to the theoretical predictions.