John E Mcdermid

Structure and metrology for an analog testability bus

This paper gives a proposal for an analog testability bus that could be used as the basis for a standard such as IEEE P1149.4. The proposed testability structure is imposed on the I/O pin cells of the analog and mixed technology ICs. It is a superset of the existing IEEE/ANSI 1149.1 testability standard for digital ICs and is intended to cooperate with it. This allows for the testing of interconnect failures such as shorts and opens, the testing of discrete analog components and networks between ICs, and supports the testing of analog functions within the ICs themselves. This paper is a companion to the result of a cooperative effort between AT&T, Ford Motor, Hewlett-Packard, Motorola and the University of Colorado at Colorado Springs.<<ETX>>

Limited access testing: IEEE 1149.4-instrumentation and methods

The IEEE 1149.4 standard is now poised for inclusion in a new generation of products. Successful application of this important new standard will depend on the availability of supporting methods and instrumentation. While the standard supplies a common architecture, the test engineer must now supply both method and instrumentation. This paper describes proven instrumentation concepts used to demonstrate IEEE 1149.4 measurements on the MEI test chip. Additionally, the paper discusses how current-stimulus and voltage-measurement techniques can be used to diagnose faulty components in medium sized networks of 75 to 150 components. IEEE 1149.4 tests can be automatically generated rather than hand crafted as in functional testing. Unlike digital resting, the technique does not use fault models. Correct operation is found by examining the deviation from nominal performance, greatly simplifying the test development task.