John Giacomoni
University of Colorado Boulder
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Publication
Featured researches published by John Giacomoni.
acm sigplan symposium on principles and practice of parallel programming | 2008
John Giacomoni; Tipp Moseley; Manish Vachharajani
Low overhead core-to-core communication is critical for efficient pipeline-parallel software applications. This paper presents FastForward, a cache-optimized single-producer/single-consumer concurrent lock-free queue for pipeline parallelism on multicore architectures, with weak to strongly ordered consistency models. Enqueue and dequeue times on a 2.66 GHz Opteron 2218 based system are as low as 28.5 ns, up to 5x faster than the next best solution. FastForwards effectiveness is demonstrated for real applications by applying it to line-rate soft network processing on Gigabit Ethernet with general purpose commodity hardware.
First IEEE International Symposium on New Frontiers in Dynamic Spectrum Access Networks, 2005. DySPAN 2005. | 2005
John Giacomoni; Douglas C. Sicker
Certification and assurance processes have historically exhibited difficulties when there exists the potential for significant non-functional attributes. We define a non-functional attribute as a condition where the cause-effect behavior cannot readily be specified. Complex systems commonly exhibit such non-functional attributes due to the exceedingly large potential state space. In such systems, analysis based on formal methods becomes very difficult and emergent behaviors (or malicious behaviors that exploit non-functional attributes) can lead to a variety of unintended consequences-some benign and others harmful. Simply put, it is difficult to assure the behavior of a complex system. The shift towards highly flexible and adaptive software defined radios creates a potential complex system problem, and thereby exposes certain assurance and certification challenges for the present regulatory processes. We use certification experiences from the security community to motivate and highlight potential difficulties that may arise within the software defined radio (SDR) space. We then recommend some steps that limit or account for these difficulties
international conference on parallel architectures and compilation techniques | 2008
Graham D. Price; John Giacomoni; Manish Vachharajani
This paper presents ParaMeter, an interactive program analysis and visualization system for large traces. Using ParaMeter, a software developer can locate and analyze regions of code that may yield to parallelization efforts and to possibly extract performance from multicore hardware. The key contributions in the paper are (1) a method to use interactive visualization of traces to find and exploit parallelism, (2) interactive-speed visualization of large-scale trace dependencies, (3) interactive-speed visualization of code interactions, and (4) a BDD variable ordering for BDD-compressed traces that results in fast visualization, fast analysis, and good compression. ParaMeters effectiveness is demonstrated by finding and exploiting parallelism in 175.vpr. Measurements of ParaMeters visualization algorithms show that they are up to seventy-five thousand times faster than prior approaches.
architectures for networking and communications systems | 2007
John Giacomoni; John K. Bennett; Antonio Carzaniga; Douglas C. Sicker; Manish Vachharajani; Alexander L. Wolf
Network processors provide an economical programmable platform to handle the high throughput and frame rates of modern and next-generation communication systems. However, these platforms have exchanged general-purpose capabilities for performance. This paper presents an alternative; a software network processor (Soft-NP) framework using commodity general-purpose platforms capable of high-rate and throughput sequential frame processing compatible with high-level languages and general-purpose operating systems. A cache-optimized concurrent lock free queue provides the necessary low-overhead core-to-core communication for sustained sequential frame processing beyond the realized 1.41 million frames per second (Gigabit Ethernet) while permitting perframe processing time expansion with pipeline parallelism.
international conference on parallel architectures and compilation techniques | 2007
John Giacomoni; Tipp Moseley; Manish Vachharajani
High-rate core-to-core communication is critical for efficient pipeline-parallel software architectures. This paper introduces FastForward, a software-only low-overhead high-rate queue algorithm for pipeline parallelism on multicore architectures. FastForward uses an architecturally- tuned domain-specific adaptation of concurrent lock-free queues to provide low-latency and low-overhead core-to- core communication. Enqueue and dequeue times on a 2 GHz Opteron 270 based system are as low as 36 ns, up to 4x faster than Lamports solution.
Archive | 2013
Manish Vachharajani; John Giacomoni
Archive | 2013
John Giacomoni; Manish Vachharajani
Archive | 2013
Manish Vachharajani; John Giacomoni
Archive | 2013
John Giacomoni; Manish Vachharajani; Mark Terrel
Archive | 2013
John Giacomoni; Manish Vachharajani