John Glossner

A software-defined communications baseband design

Software-defined radios offer a programmable and dynamically reconfigurable method of reusing hardware to implement the physical layer processing of multiple communications systems. An SDR can dynamically change protocols and update communications systems over the air as a service provider allows. In this article we discuss a baseband solution for an SDR system and describe a 2 Mb/s WCDMA design with GSM/GPRS and 802.11b capability that executes all physical layer processing completely in software. We describe the WCDMA communications protocols with a focus on latency reduction and unique implementation techniques. We also describe the underlying technology that enables software execution. Our solution is programmed in C and executed on a multithreaded processor in real time.

The sandbridge SB3011 platform

This paper describes the Sandbridge Sandblaster real-time software-defined radio platform. Specifically, we describe the SB3011 system-on-a-chip multiprocessor. We describe the software development system that enables real-time execution of communications and multimedia applications. We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding. Each processor core achieves 600 MHz at 0.9 V operation while typically dissipating 75 mW in 90 nm technology. The entire chip typically dissipates less than 500 mW at 0.9 V.

A Low-Power Multithreaded Processor for Software Defined Radio

Embedded digital signal processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the processor’s architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the processor’s programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for a wide variety of digital signal processing and multimedia applications.

The sandbridge SB3011 SDR platform

This paper describes the Sandbridge Sandblaster real-time software defined radio platform. Specifically we describe the SB301I system on a chip multiprocessor. We describe the software development system that enables real-time execution of communications and multimedia applications. We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding. All results presented are from completely implemented systems from RF through baseband

Instruction set extensions for Reed-Solomon encoding and decoding

Reed-Solomon codes are an important class of error correcting codes used in many applications related to communications and digital storage. The fundamental operations in Reed-Solomon encoding and decoding involve Galois field arithmetic which is not directly supported in general purpose processors. On the other hand, pure hardware implementations of Reed-Solomon coders are not programmable. In this paper, we present a novel algorithm to perform Reed-Solomon encoding. We also propose four new instructions for Galois field arithmetic. We show that by using the instructions, we can speedup Reed-Solomon decoding by a factor of 12 compared to a pure software approach, while still maintaining programmability.

Parallel saturating fractional arithmetic units

This paper describes the designs of a saturating adder multiplier single MAC unit, and dual MAC unit with single cycle latencies. The dual MAC unit can perform two saturating MAC operations in parallel and accumulate the results with saturation. Specialized saturation logic ensures that the output of the dual MAC unit is identical to the result of the operations performed serially with saturation after each multiplication and each addition.

Implementation of H.264 decoder on Sandblaster DSP

This paper presents the optimization techniques and results of implementing the H.264/AVC baseline profile decoder in software on the Sandblaster digital signal processor. It has been implemented in ANSI C and optimized to exploit the architectural features of the processor. The software implementation enables the reusability of the processor and lowers the development costs.

Software implementation of WiMAX on the sandbridge sandblaster platform

This paper describes a Sandbridge Sandblaster system implementation including both hardware and software elements for a WiMAX 802.16e system. The system is implemented on the fully functional multithreaded Sandblaster multiprocessor SB3010 SoC chip. The entire communication protocol, physical layer and MAC, has been implemented in software using pure ANSI C programming language and it executes in real time. In this paper, we also present a radio propagation analysis specific to the Samos island at the workshop location, and the DSP execution performance.

Towards a very high bandwidth wireless battery powered device

We discuss the hardware and software challenges in building a 2 Mbit per second wireless battery powered communications device. Of primary importance is power dissipation. To achieve aggressive power targets, a host of new techniques are required at all levels of the design hierarchy. Techniques for parallelizing saturating arithmetic will become important because of the software optimizations they enable. Highly configurable programmable structures will enable multiprotocol SOC solutions. To program complex SOCs, new compiler techniques will be required. Hardware implementations will need to be intimately aware of these software techniques. In particular both signal processing code written in C and control code written in Java will drive new compilation techniques to enable broadband 3G wireless systems.

Instruction set extensions for software defined radio

Software defined radios provide programmable solutions for implementing the physical layer processing of multiple communication standards. Mobile devices implementing these standards require high-performance processors to perform high-bandwidth physical layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including cyclic redundancy checking, convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. We also present hardware designs for implementing these extensions, along with estimates of their area, critical path delay, and power consumption. The performance benefits of these extensions are evaluated using a supercomputer-class vectorizing compiler and the Sandblaster low-power multithreaded processor for software defined radio. The proposed instruction set extensions provide significant performance improvements at relatively low cost, while maintaining a high degree of programmability.