John J. Granacki

The architecture of the DIVA processing-in-memory chip

The DIVA (Data IntensiVe Architecture) system incorporates a collection of Processing-In-Memory (PIM) chips as smart-memory co-processors to a conventional microprocessor. We have recently fabricated prototype DIVA PIMs. These chips represent the first smart-memory devices designed to support virtual addressing and capable of executing multiple threads of control. In this paper, we describe the prototype PIM architecture. We emphasize three unique features of DIVA PIMs, namely, the memory interface to the host processor, the 256-bit wide datapaths for exploiting on-chip bandwidth, and the address translation unit. We present detailed simulation results on eight benchmark applications. When just a single PIM chip is used, we achieve an average speedup of 3.3X over host-only execution, due to lower memory stall times and increased fine-grain parallelism. These 1-PIM results suggest that a PIM-based architecture with many such chips yields significantly higher performance than a multiprocessor of a similar scale and at a much reduced hardware cost.

Restoring lost cognitive function

A prosthetic device that functions in a biomimetic manner to replace information transmission between cortical brain regions is considered. In such a prosthesis, damaged CNS neurons is replaced with a biomimetic system comprised of silicon neurons. The replacement silicon neurons would have functional properties specific to those of the damaged neurons and would both receive as inputs and send as outputs electrical activity to regions of the brain with which the damaged region previously communicated. Thus, the class of prosthesis proposed is one that would replace the computational function of the damaged brain and restore the transmission of that computational result to other regions of the nervous system.

A Hippocampal Cognitive Prosthesis: Multi-Input, Multi-Output Nonlinear Modeling and VLSI Implementation

This paper describes the development of a cognitive prosthesis designed to restore the ability to form new long-term memories typically lost after damage to the hippocampus. The animal model used is delayed nonmatch-to-sample (DNMS) behavior in the rat, and the “core” of the prosthesis is a biomimetic multi-input/multi-output (MIMO) nonlinear model that provides the capability for predicting spatio-temporal spike train output of hippocampus (CA1) based on spatio-temporal spike train inputs recorded presynaptically to CA1 (e.g., CA3). We demonstrate the capability of the MIMO model for highly accurate predictions of CA1 coded memories that can be made on a single-trial basis and in real-time. When hippocampal CA1 function is blocked and long-term memory formation is lost, successful DNMS behavior also is abolished. However, when MIMO model predictions are used to reinstate CA1 memory-related activity by driving spatio-temporal electrical stimulation of hippocampal output to mimic the patterns of activity observed in control conditions, successful DNMS behavior is restored. We also outline the design in very-large-scale integration for a hardware implementation of a 16-input, 16-output MIMO model, along with spike sorting, amplification, and other functions necessary for a total system, when coupled together with electrode arrays to record extracellularly from populations of hippocampal neurons, that can serve as a cognitive prosthesis in behaving animals.

The ADAM Advanced Design Automation System: Overview, Planner and Natural Language Interface

This paper describes ADAM, an integrated Advanced Design AutoMation system, with focus on the knowledge-based synthesis subsystem. Working parts of this subsystem include a number of design activities and utilities, and a unified, multidimensional, hierarchical design representation. Two aspects of the synthesis subsystem are described in detail: the design planner and the natural language interface. The planner builds a plan for synthesis and analysis activities, drawing inferences from a knowledge base represented by a semantic net. The natural language interface accepts system-level behavioral specifications. Both of these packages are currently being implemented.

DEFACTO: A Design Environment for Adaptive Computing Technology

The lack of high-level design tools hampers the widespread adoption of adaptive computing systems. Application developers have to master a wide range of functions, from the high-level architecture design, to the timing of actual control and data signals. In this paper we describe DEFACTO, an end-to-end design environment aimed at bridging the gap in tools for adaptive computing by bringing together parallelizing compiler technology and synthesis techniques.

Implantable biomimetic microelectronic systems design

In this article, design examples will be presented for a biomimetic microelectronic system for a retinal prosthesis that electrically stimulates the retinal neurons. The system replaces the functionality of vision in blind patients affected by retinitis pigmentosa and age-related macular degeneration. The components and signal processing needed for a cortical prosthesis are described. Integration of all the components of a wireless biomimetic microelectronic system, such as input signal conditioning, power telemetry, data telemetry, stimulation amplifier and control circuitry (microstimulator), and a neural recording and processing device, into a single chip or a package is a tremendous challenge, requiring innovative approaches at both circuit and system levels and consideration of the multiple trade-offs between size, power consumption, flexibility in functionality, and reliability of the microelectronics. The chips described in this paper are prototypes for testing their implemented functionalities. The die sizes do not reflect the actual size of the implant. When the microelectronics are finally integrated, the circuits will be optimized to minimize the area. The use of submicron CMOS technology will also help reduce the die area. It should be noted that the biocompatible package encapsulating the electronics will increase the implant size.

Novel Charge-Metering Stimulus Amplifier for Biomimetic Implantable Prosthesis

A novel charge-metering stimulus amplifier is proposed for high performance neural prosthesis stimulation. The new charge-based approach with feedback has low charge error 0.5%, low charge imbalance 0.2%, and high power efficiency. Charge-metering stimulus amplifier can be implemented using advanced 0.18mum CMOS technology and is compatible with mixed-signal system-on-a-chip (SoC) implantable devices. It also has the capability to monitor the electrode-tissue contact quality and estimate the interface impedance in real-time for robust stimulation.

Representation of control and timing behavior with applications to interface synthesis

The authors describe a formalism for the representation of interface behavior which can be used for high-level synthesis by a design automation system. The Design Data Structure can represent the many facets of interface behavior in a unified way, including timing constraints, synchronous and asynchronous signals, control flow, and data manipulation. Its descriptive power is more complete than some other formalisms in use, including event and annotated data-flow graphs. The representations described here can be used by data path synthesizers to capture more complex timing information than is typically handled and to separate control from data manipulation information to produce cleaner data flow graphs. The Design Data Structure has been used successfully as an internal representation for a natural-language interface for system specification.<<ETX>>

PHRAN-SPAN: A Natural Language Interface for System Specifications

This paper describes a natural language interface, PHRAN-SPAN, for specifying the abstract behavior of digital systems in restricted English text. A neutral formal representation for the behavior is described using the USC Design Data Structure. A small set of concepts that characterize digital system behavior are presented using this representation. Finally, an intermediate representation based on Conceptual Dependencies is presented. Its use with a semantic-based parser to translate from English to the formal representation is illustrated by a series of examples.

CMOS 12 bits 50kS/s micropower SAR and dual-slope hybrid ADC

In this paper a 12 bits 50kS/s micropower hybrid ADC is proposed for biomimetic microelectronic systems using 0.18um CMOS process. The hybrid ADC combines SAR and dual-slope architectures to achieve 12 bits, power consumption 60uW, and small silicon die size. This hybrid ADC shows very good figure-of-merits (FOM) on both power consumption and silicon die size compared with conventional low power SAR ADC. A fully differential GmC integrator is proposed for the dual-slope operation with low voltage discrete-time CMFB.