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John J. Seliskar

LSI Corporation

Publication

Featured researches published by John J. Seliskar.

Archive | 1999

Low threshold voltage MOS transistor and method of manufacture

John J. Seliskar

Archive | 1999

Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET

John J. Seliskar; Verne Hornback; David W. Daniel

Archive | 1996

Integrated circuit device having a capacitor with the dielectric peripheral region being greater than the dielectric central region

John J. Seliskar; Derryl D. J. Allman; John W. Gregory; James P. Yakura; Dim Lee Kwong

Archive | 2000

Fully-depleted, fully-inverted, short-length and vertical channel, dual-gate, cmos fet

Michael F. Chisholm; David W. Daniel; Verne Hornback; John J. Seliskar

Archive | 1998

MeV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor

John J. Seliskar; David W. Daniel; Todd A. Randazzo

Archive | 1999

Integrated circuit device and method of making the same using chemical mechanical polishing to remove material in two layers following masking

John J. Seliskar; Derryl D. J. Allman; John W. Gregory; James P. Yakura; Dim Lee Kwong

Archive | 1997

Process for fabricating a moderate-depth diffused emitter bipolar transistor in a BICMOS device without using an additional mask

Todd A. Randazzo; John J. Seliskar

Archive | 1997

Integrated circuit device and method of making the same

John J. Seliskar; Derryl D. J. Allman; John W. Gregory; James P. Yakura; Dim Lee Kwong

Archive | 1998

Bipolar transistor with reduced vertical collector resistance

John J. Seliskar; David W. Daniel; Todd A. Randazzo

Archive | 1998

Process for fabricating a diffused emitter bipolar transistor

Todd A. Randazzo; John J. Seliskar

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