John Kuehne

Single-wafer integrated semiconductor device processing

The authors present an overview of various single-wafer fabrication techniques for integrated processing of microelectronic devices. Numerous processing modules, sensors, and associated fabrication processes have been developed for advanced semiconductor device manufacturing. The combination of single-wafer processing, cluster tools, sensors, and advanced factory control/computer-integrated manufacturing techniques provides a capability for flexible fast-cycle-time device manufacturing. Specific developments and results are described in the areas of dry/vapor-phase surface cleaning, epitaxy, plasma processing, rapid thermal processing, and in situ sensors. An integrated sub-half micrometer CMOS technology based on these single-wafer fabrication methods including rapid thermal processing is also described. >

Quantitative inelastic tunneling spectroscopy in the silicon metal-oxide-semiconductor system

A dual temperature method has been developed for subtracting the 77 K thermally smoothed background from 4.2 K inelastic electron tunneling spectra of ultrathin dielectric metal-insulator-semiconductor junctions. A mode resolving method applied to the remaining spectrum clearly identifies electrode and insulator vibrational modes. The ability to track these relative mode positions and amplitudes shows promise as a unique interface analysis and process diagnostic method. Results are reported on polycrystalline silicon gate, 1.5-nm-thick oxide devices fabricated on 1–10 Ω cm, N-type, (100) silicon substrates by a standard industrial process sequence.

Thin fluorinated gate dielectrics grown by rapid thermal processing in O/sub 2/ with diluted NF/sub 3/

The authors report the application of rapid thermal processing (RTP) to the fabrication of ultrathin ( approximately 10 nm) high-quality fluorinated oxides in O/sub 2/+NF/sub 3/ (100 ppm diluted in N/sub 2/). NF/sub 3/ was used as the F source gas and was introduced either prior to rapid thermal oxidation (RTO) or with O/sub 2/ during the initial stage of RTO. The oxidation rate was enhanced because of the presence of NF/sub 3/. In addition, F depth profiles in fluorinated oxides were dependent upon the process conditions. The electrical characteristics of MOS capacitors have been studied and correlated with the chemical properties. The initial interface state density (D/sub t/) was found to decrease with F incorporation. The results suggest that the interfacial F incorporation plays a major role in determining the interface hardness for both hot-electron and radiation damages. >

Radiation hardened metal‐oxide‐semiconductor devices with gate dielectrics grown by rapid thermal processing in O2 with diluted NF3

Radiation‐hardened, fluorinated gate oxides have been obtained by rapid thermal processing of silicon in O2 with diluted NF3. Diluted NF3 is used as a source of fluorine and is introduced during the initial stage of rapid thermal processing. It is found that optimum amounts of fluorine incorporated at the Si/SiO2 interface improve resistance against x‐ray radiation; however, excessive amounts of fluorine degrade the radiation hardness.

MOS characteristics of fluorinated gate dielectrics grown by rapid thermal processing in O/sub 2/ with diluted NF/sub 3/

Rapid thermal processing (RTP) was applied to the fabrication of the ultrathin ( approximately 10 nm) high-quality fluorinated oxides in O/sub 2/+NF/sub 3/. NF/sub 3/ (diluted in N/sub 2/) was used as the F source gas and was introduced either prior to rapid thermal oxidation (RTO) or with O/sub 2/ during the initial stage of RTO. The electrical characteristics of MOS capacitors have been studied and correlated with the chemical properties. It was found that SiO/sub 2/ with a small amount of F incorporated shows reduced interface state generation under F-N injection, whereas excessive F incorporation is detrimental.<<ETX>>

Fluorinated thin SiO2 grown by rapid thermal processing

High quality ultrathin fluorinated gate oxides have been grown for the first time by rapid thermal processing in diluted NF3 and O2. The chemical and electrical properties of fluorinated oxides have been studied as a function of growth conditions.

Fast-cycle-time single-wafer IC manufacturing

Abstract This paper presents a demonstration of the total use of RTP for fast-cycle-time semiconductor IC production. The feasibility of eliminating batch processing for CMOS IC fabrication has been shown. Our fast-cycle-time flexible single-wafer minifactory contains 34 single-wafer processors having various combinations of at least 9 different in-situ process monitoring and control sensors. Forty device fabrication processes are done with these systems, the majority being Advanced Vacuum Processors (AVPs). Multiple combinations of process energy sources and in-situ sensors are used to perform many process steps. Vacuum wafer cassettes are used for transporting wafers in a clean environment between machines. All of the AVPs are driven and supervised by a computer-integrated manufacturing (CIM) system, with unit process recipe specifications passed to the AVP host computer for process execution and control. More than 40 AVP systems have been designed and built for applications in TIs advanced silicon integrated circuit and HgCdTe detector technologies. Rapid thermal processes have been developed for all the thermal fabrication steps required in two 0.35 μm CMOS technologies. These processes include thin dielectric growth (dry and wet rapid thermal oxidations), high-pressure field oxidation, high-pressure BPSG reflow, source/drain and gate anneals. CMOS well formation, TiN/TiSi2 react & anneal, forming-gas anneal, and rapid thermal chemical-vapor deposition (RTCVD) processes for amorphous silicon, polysilicon, tungsten, silicon dioxide, and silicon nitride. These RTPs cover a processing temperature range of 450°–1100°C. An integrated sensor system will also be presented for rapid thermal process control. The lamp-heated reactors employ multi-zone axisymmetric illuminators and noinvasive in-situ sensors for real-time process uniformity control and process/equipment diagnostics. Various modes of sensor fusion have been implemented for improved equipment/process control performance. Improved RTP control has been established throughout the integrated CMOS flows using a customized backside seal structure on epitaxial wafers. Complete sub-half-micron CMOS process integration and device manufacturing have been successfully demonstrated with all-RTP thermal processing. Source/drain RTP was shown to decrease the effect of back-end processing on both salicided and unsalicided CMOS 0.25 μm devices.

In-situ spectral ellipsometry for real-time thickness measurement and control

A polarization modulated spectroscopic ellipsometer (SE) is used in situ to measure the thicknesses of films in real time during processing. These thicknesses are used for adaptive control during single-wafer processing. Using the speed of phase modulation, multichannel detection, and digital signal processing techniques, this ellipsometer is capable of acquiring spectra in less than 75 ms. Efficient algorithms were developed for determining layer parameters (thicknesses and composition) from the measured spectra of multilayer film stacks in one second or less. The measured thicknesses and etch rates are used to anticipate interfaces in multiple layer stacks and control process end points. A repeatability gauge study was performed using this in situ SE and a commercial single-wavelength ellipsometer (SWE) on thermally grown silicon dioxide on silicon wafers. Data was obtained on each instrument over an oxide thickness range from 60 to 250 angstroms. The total repeatability for the in situ SE measurements was 0.26 angstroms (1.6 angstroms 6-sigma) over this thickness range.

Nitrogen Profile Engineering in Thin Gate Oxides

In order to prevent boron penetration in PMOS transistors without degrading channel mobility, it is necessary to engineer the distribution of nitrogen introduced into the gate oxide. We have investigated methods of engineering this distribution using nitric oxide (NO) gas in an RTP system to thermally nitride ultra-thin gate oxides. In one approach, the gate oxide is simultaneously grown and nitrided in a mixture of nitric oxide and oxygen. For a 40 A film, SIMS depth profiling shows that this process moves the nitrogen peak into the bulk of the oxide away from the oxide silicon interface. In another approach, an 11 A chemical oxide produced by a standard pre-furnace wet clean is nitrided in NO at 800 deg. C. This film is subsequently reoxidized in either oxygen or steam. For an 1100 deg. C., 120 sec RTP reoxidation in oxygen, the final film thickness is 41 A. The nitrogen has a peak concentration of 5 at. % and the peak is located in the oxide 25 Afrom the oxide/silicon interface. Ramped voltage breakdown testing was carried out on MOS capacitors built using reoxidized NO nitrided films. They have breakdown characteristics that are equivalent to conventional furnace grown oxides. These films show considerable promise as gate dielectrics for CMOS technologies at geometries of 0.25um and below.

The use of rapid thermal processing to improve performance of sub-half micron CMOS with and without salicide

The dependence of performance and parasitic resistances on source/drain implant anneal conditions and on back-end-of-line maximum temperature is evaluated for (1) salicided CMOS using n/sup +//p/sup +/ poly gates with surface channel PMOS and for (2) unsalicided CMOS using all n/sup +/ poly gates with buried channel PMOS. The gate oxide thickness used is 6 nm. Both the NMOS and PMOS effective channel lengths are near 0.25 mu m. The results show that CMOS circuit design can include wide transistors and asymmetrically placed contacts if salicide is used with RTP anneal of source/drain and back-end-of-line temperatures no higher than 725 C.<<ETX>>