John Lau

Acceleration models, constitutive equations, and reliability of lead-free solders and joints

Abst ract A set of accclcration niodels for lead-frec solder joints is proposed and discussed in this shidy. Useful equations for the acceleration models, life distribution. and failure m e are also provided. Furthennorc, methods for selecting the acceleration factor are discussed. In addition. non-lincar 3D creep analyscs of the 256-pin plastic ball grid array PCB (printed circuit board) assembly are presented. The solder joints are made of 95.5wt%Sn-j .9wt%Ag-O.~~~tY~u lead-free soldcr. The leadfree results will be coinparcd to those with Sn-Pb solder joints.

Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board

In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, shear creep strain history, and creep strain density range at the corner solder joint are presented for a better understanding of the thermal-mechanical behavior of the lead-free solder bumped WLCSP on microvia buildup PCB assemblies.

Design for lead‐free solder joint reliability of high‐density packages

The lead‐free solder joint reliability of several printed circuit board mounted high‐density packages, when subjected to temperature cycling was investigated by finite element modelling. The packages were a 256‐pin plastic ball grid array (PBGA), a 388‐pin PBGA, and a 1657‐pin ceramic column grid array. Emphasis was placed on the determination of the creep responses (e.g. stress, strain, and strain energy density) of the lead‐free solder joints of these packages.

Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)

The creep analyses of solder-bumped wafer level chip scale package (WLCSP) on build-up printed circuit board (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are assumed to follow the Garofalo-Arrhenius creep constitutive law. The shear stress and creep shear strain hysteresis loops, shear stress range, creep shear strain range, and creep strain energy density range at different locations in the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of the solder-bumped WLCSP on build-up PCB with microvias. It is found that, due to the large coefficient of thermal expansion of the build-up resin, the effects of thickness of the PCB with microvia build-up layer become much more significant than that without the microvia build-up layer.

Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability

Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the, important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layer on the solder joint reliability of WLCSP on printed circuit board (PCB) through the creep responses such as the deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped with pad-redistribution WLCSPs are considered in this study.

Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies

The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by fracture mechanics with finite element method. Furthermore, an empirical equation for predicting the thermal-fatigue life of flip chip solder joints is proposed.

Solder joint reliability of cavity‐down plastic ball grid array assemblies

A computational model was established in this study to simulate cavity‐down plastic ball grid array (PBGA) assemblies. Stress analysis was performed to investigate the solder joint reliability of a PBGA‐PCB (printed circuit board) assembly. The packages under investigation had two different body sizes and two kinds of ball population. The diagonal cross‐section of the assembly was modeled by plane‐strain elements and was subjected to a uniform thermal loading. The solder joints were stressed due to the mismatch of the assembly’s coefficient of thermal expansion (CTE). The accumulated effective plastic strain was evaluated as an index for the reliability of solder joints. Effects on solder joint reliability such as package size and ball population were identified. Furthermore, it was found that, unlike conventional PBGA assemblies, the outermost solder ball has the highest plastic strain for all cases in the present study. This peculiar phenomenon was further discussed with the consideration of package deformation.

Reliability testing and data analysis of lead‐free solder joints for high‐density packages

Temperature cycling tests, and statistical analysis of the results, for various high‐density packages on printed‐circuit boards with Sn‐Cu hot‐air solder levelling, electroless nickel‐immersion gold, and organic solder preservative finishes are investigated in this study. Emphasis is placed on the determination of the life distribution and reliability of the lead‐free solder joints of these high‐density package assemblies while they are subjected to temperature cycling conditions. A data acquisition system, the relevant failure criterion, and the data extraction method will be presented and examined. The life test data are best fitted to the Weibull distribution. Also, the sample mean, population mean, sample characteristic life, true characteristic life, sample Weibull slope, and true Weibull slope for some of the high‐density packages are provided and discussed. Furthermore, the relationship between the reliability and the confidence limits for a life distribution is established. Finally, the confidence levels for comparing the quality (mean life) of lead‐free solder joints of high‐density packages are determined.

Effects of underfill encapsulant on the mechanical and electrical performance of a functional flip chip device

The curing conditions and material properties such as the coefficient of thermal expansion, glass transition temperature, Youngs modulus, and moisture content of four different underfill encapsulants with different size and content of filler and epoxy are measured. The effects of these underfills on the flow rate, mechanical performance, and electrical performance of a solder-bumped functional flip chip on an organic substrate are studied.

Effects of voids on bump chip carrier (BCC++) solder joint reliability

In this study, the effects of voids on the solder joint reliability of bump chip carrier (BCC++) packages on a printed circuit board are investigated. Emphasis is placed on the void size, void location, and void percentage. The solder is assumed to obey the Garofalo-Arrhenius creep constitutive equation. A total of 12 different cases are studied. In addition, the effects of voids on the crack growth in the BCC++ solder joint are studied by the fracture mechanics method. Emphasis is placed on the demonstration that a crack in the solder joint may be stopped by a void in front of it.