John N. Helbert

Lithographic Process Development for High Numerical Aperture I-Line Steppers

A high contrast single layer i-line resist process was developed using Aspect Systems 9 resist for a GCA 5X wafer stepper equipped with a Tropel 20 mm diameter, 0.40 NA lens. The process development sequence is described, where surface response experiments are used to evaluate the effects on resist contrast of process factors. These factors include prebake time and temperature, post exposure bake time and temperature, metal-ion free developer concentration, develop time, and develop temperature. Contrast is found to depend upon standing wave interference. Results of a factorial comparison of the single layer process for critical dimension control with and without CEM 388 made for site-to-site and wafer-to-wafer variations yielded similar results. SEM micrographs for the optimized single layer process illustrate near verticle resist profiles with good depth of focus latitude, and agree well with PROSIMulations except under large defocus conditions. The optimized single layer resist process has been employed to evaluate a new Tropel 20 mm diameter, 0.40 numerical aperture, i-line lens with good results.

Improving metrology signal-to-noise on grainy overlay features

High temperature metal deposition produces large grain size and a highly visible surface morphology due to grain boundaries. When an interconnect layer photoresist pattern is aligned, grainy metal results in noisy signals from optical metrology equipment. The overlay metrology tool hardware and software configuration and target design must be optimized to obtain the best possible signal-to-noise. A powerful metric is developed herein to single out the noise component due to the overlay target image distortions. This methodology is suitable to a production environment. A variety of techniques based upon the target noise metric, including designed experiments, are employed to optimize the overlay measurements configuration.

Issues and Trends Affecting Lithography Tool Selection Strategy

Publisher Summary The definition of the method to be used for the selection of an optimum lithography system is the purpose of this chapter. There are many factors in the selection process. The primary factor is the technical requirements: Are the equipment and process capable of defining and registering the features we need to produce. In addition, integrated circuit (IC) fabrication requires performing a long sequence of many complex processes. Lithography, which recurs typically as many as ten to thirty-plus times for a given device flow, is the most important of these complex processes as it is used to define the dimensions, doping, and interconnection of each segment of each device. Literally, this indirect process defines nearly all of the working elements for the IC device. This chapter focuses on the view that lithography methods (printing patterns) are pursued for the singular purpose of manufacturing IC chips in the highly competitive commercial sector, and it attempts to delineate the factors determining lithographic tool selection.

Production metrology and control of color filter array photolithography for CMOS imagers

The color filter array (CFA) for an image-producing semiconductor device is composed of patterned red-, and green- and blue-colored photoresist structures. CFA photolithography is rather different from that of most semiconductor process levels.

2 – Resist Technology—Design, Processing, and Applications

Publisher Summary The emphasis of this chapter is placed on applications of the technology to the manufacturing of prototype and production integrated circuit devices. Furthermore, a greater emphasis is placed upon empirical resist process development to achieve reproducible and statistically-controlled resist manufacturing processes. In addition, the objective of this chapter is to provide a users view of resist/lithographic process technology. Photolithography technology, the combination of the exposure tool, and the image transfer process, is vital to integrated circuit fabrication, or more generally, semiconductor device manufacturing. Nearly every primary device fabrication step requires a process-compatible masking layer, which is capable of providing a desired circuit level pattern. This indirect patterning is required because either the layer is not directly patternable technologically, or it cannot be accomplished economically.

Lithographic impact of thin film effects on advanced BIMOS semiconductor device layer structures

Variations in wafer substrate film stacks can have a significant effect upon the resist critical dimension (CD) and exposure level for layers patterned to fabricate advanced four level metal BIMOS devices. In the fabrication of these VLSI devices, patterning is frequently performed on film stacks of varying thickness and optical properties. PROLITH was used to simulate lithography behavior on actual device film stacks, and the results compared favorably to data collected from actual product wafers. Simulations can be used to accurately predict the exposure changes needed to compensate for changes in film thickness and film stack upon CD. Good agreement was obtained for most cases studied, with less than 3% deviation between the experimental and simulated results being typical. In most cases, the PROLITH simulated data and empirically determined results were in good agreement. Thin film reflectivity is also observed to have a strong influence on CD variation. In via patterning experiments, for example, vias printed with only resist exhibited “reflective notching dominated” CD 3-sigma variation of 0.10 pm greater than that observed where an optimized ARC process was employed under the resist to minimize substrate reflectivity. The significant improvements in CD variation have been generally correlated with reductions and/or optimizations in substrate reflectivity. Electrical probe CD data for backend metal layers has also been evaluated for thin film notching behavior, and as seen for via layer notching, the CD variation is minimized by applying the results from PROLITH reflectivity analysis. The significant improvements in CD variation have been correlated with the reduction and optimization of substrate reflectivity, which is determined by the combination(s) of dielectric and resist contributors.