John P. Karidis

Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling

Phase Change Memory (PCM) is an emerging memory technology that can increase main memory capacity in a cost-effective and power-efficient manner. However, PCM cells can endure only a maximum of 107-108 writes, making a PCM based system have a lifetime of only a few years under ideal conditions. Furthermore, we show that non-uniformity in writes to different cells reduces the achievable lifetime of PCM system by 20×. Writes to PCM cells can be made uniform with Wear-Leveling. Unfortunately, existing wear-leveling techniques require large storage tables and indirection, resulting in significant area and latency overheads. We propose Start-Gap, a simple, novel, and effective wear-leveling technique that uses only two registers. By combining Start-Gap with simple address-space randomization techniques we show that the achievable lifetime of the baseline 16 GB PCM-based system is boosted from 5% (with no wear-leveling) to 97% of the theoretical maximum, while incurring a total storage overhead of less than 13 bytes and obviating the latency overhead of accessing large tables. We also analyze the security vulnerabilities for memory systems that have limited write endurance, showing that under adversarial settings, a PCM-based system can fail in less than one minute. We provide a simple extension to Start-Gap that makes PCM-based systems robust to such malicious attacks.

Morphable memory system: a robust architecture for exploiting multi-level phase change memories

Phase Change Memory (PCM) is emerging as a scalable and power efficient technology to architect future main memory systems. The scalability of PCM is enhanced by the property that PCM devices can store multiple bits per cell. While such Multi-Level Cell (MLC) devices can offer high density, this benefit comes at the expense of increased read latency, which can cause significant performance degradation. This paper proposes Morphable Memory System (MMS), a robust architecture for efficiently incorporating MLC PCM devices in main memory. MMS is based on observation that memory requirement varies between workloads, and systems are typically over-provisioned in terms of memory capacity. So, during a phase of low memory usage, some of the MLC devices can be operated at fewer bits per cell to obtain lower latency. When the workload requires full memory capacity, these devices can be restored to high density MLC operation to have full main-memory capacity. We provide the runtime monitors, the hardware-OS interface, and the detailed mechanism for implementing MMS. Our evaluations on an 8-core 8GB MLC PCM-based system show that MMS provides, on average, low latency access for 95% of all memory requests, thereby improving overall system performance by 40%.

Autonomic personal computing

Autonomic personal computing is personal computing on autonomic computing platforms. Its goals combine those of personal computing with those of autonomic computing. The challenge of personal autonomic computing is to simplify and enhance the end-user experience, delighting the user by anticipating his or her needs in the face of a complex, dynamic, and uncertain environment. In this paper we identify the key technologies that enable autonomic behavior as distinguished from fault-tolerant behavior. We give some examples of current autonomic behavior and some general considerations for an architecture that supports autonomic personal computing. We identify its challenges to standards and technology developers and conclude with some guidance for future work.

A remote center of motion robotic arm for computer assisted surgery

We have designed a robotic arm based on a double parallel four bar linkage to act as an assistant in minimally invasive surgical procedures. The remote center of motion (RCM) geometry of the robot arm kinematically constraints the robot motion such that minimal translation of an instrument held by the robot takes place at the entry portal into the patientApos;s body. In addition to the two rotational degrees of freedom comprising the RCM arm, distal translation and rotation are provided to manoeuver the instrument within the patients body about an axis coincident with the RCM. An XYZ translation stage located proximal to the RCM arm provides positioning capability to establish the RCM location relative to the patients anatomy. An electronics set capable of controlling the system, as well as performing a series of safety checks to verify correct system operation, has also been designed and constructed. The robot is capable of precise positional motion. Repeatability in the ±10 micron range is demonstrated. The complete robotic system consists of the robot hardware and an IBM PC-AT based servo controller connected via a custom shared memory link to a host IBM PS/2. For laparoscopic applications, the PS/2 includes an image capture board to capture and process video camera images. A camera rotation stage has also been designed for this application. We have successfully demonstrated this system as an assistant in a laparoscopic cholecystectomy. Further applications for this system involving active tissue manipulation are under development.

Architectural design for next generation heterogeneous memory systems

New enterprise workloads requiring fast, reliable access to increasing amounts of data have pushed todays memory systems to power and capacity limits while creating bottlenecks as they ensure transactions are persistently tracked for reliability. New storage class memory technologies (such as phase change memory) have the potential to offer high capacity within latency and bandwidth ranges acceptable for a computer memory system and persistence which may help ease the system-level burden of balancing performance and reliability. This paper describes architectural options for addressing the challenges of future, heterogeneous memory systems as well as the attributes required of the next generation memory devices.

On the lifetime of multilevel memories

We study memories capable of storing multiple bits per memory cell, with the property that certain state transitions “wear” the cell. We introduce a model that is relevant for Phase Change Memory, a promising emerging nonvolatile memory technology that exhibits limitations in the number of particular write actions that one may apply to a cell before rendering it unusable. We exploit the theory of Write Efficient Memories to derive a closed form expression for the storage capacity/lifetime fundamental tradeoff for this model. We then present families of codes specialized to distinct ranges for the target lifetimes, covering the full range from moderate redundancy to an arbitrarily large lifetime increase. These codes have low implementation complexity and remarkably good performance; for example in an 8 level cell we can increase the lifetime of a memory by a factor of ten while sacrificing only 2/3 of the uncoded storage capacity of the memory.

The Hummingbird minipositioner-providing three-axis motion at 50 g's with low reactions

The Hummingbird minipositioner is a three-axis servo-mechanism designed to provide fast and accurate positioning of a low-mass probe tip on or above a nearly planar object. Peak XYZ accelerations in excess of 500 m/s/sup 2/ (50 g) are obtained, with positioning resolution under 1 mu m and a workspace of 13 by 13 by 1 mm. The system weighs 950 g and is nearly reactionless during X-Y motion to simplify integration with large-area positioners. The design of the dynamically balanced five-bar linkage assembly and the Z-actuator is presented, along with data on in-plane linkage resonances (shown to be >1 kHz) and the torque cancellation effectiveness. A typical incremental move of 5 mm with 50 g peak acceleration and a move time of 8 ms is also presented.<<ETX>>

True value: assessing and optimizing the cost of computing at the data center level

There are five main components to the cost of delivering computing in a data center: (i) the construction of the data center building itself; (ii) the power and cooling infrastructure for the data center; (iii) the acquisition cost of the servers that populate the data center; (iv) the cost of electricity to power (and cool) the servers; and (v) the cost of managing those servers. We first study the fundamental economics of operating such a data center with a model that captures the first four costs. We call these the physical cost, as it does not include the labor cost. We show that it makes economic sense to design data centers for relatively low power densities, and that increasing server utilization is an efficient way to reduce total cost of computation. We then develop a cost/performance model that includes the management cost and allows the evaluation of the optimal server size for consolidation. We show that, for a broad range of operating and cost conditions, servers with 4 to 16 processor sockets result in the lowest total cost of computing.

Adaptive endurance coding for NAND Flash

A fundamental constraint in the use of newer NAND Flash devices in the enterprise space is the low cycling endurance of such devices. As an example, the latest 2-bit MLC devices have a cycling endurance ranging from 3K to 10K program/erase cycles. Upcoming higher-density devices are expected to have even lower endurance. In this paper we propose a coding technique called Adaptive Endurance Coding (AEC) which increases the number of program/erase cycles that a Flash device can endure. The key insight leveraged by the proposed technique is the data-dependent nature of Flash cell-wear. Data-dependent wear implies that Flash chip/device lifetime can be significantly increased by converting data into bit-patterns, prior to programming, which cause minimal wear. AEC can be used to generate a capacity-wear trade-off; for compressible data, AEC can be adapted to data compressibility in order to maximize endurance gains with low system overhead costs. The technique can be implemented in the Flash device controller without requiring any hardware changes to the device itself. We present empirical results on SLC and MLC Flash chips demonstrating the improvements in retention and bit-error rate which can be obtained via this technique, and present device-level simulation results quantifying the gains achievable by the use of AEC.

The inner workings of phase change memory: Lessons from prototype PCM devices

We describe observations into the inner workings of phase change memory devices, obtained by fabrication, electrical characterization, failure analysis, and modeling of prototype phase change memory devices over the past few years. Experiments involving the RESET and SET operations, the speed of SET operations, the impact of voltage polarity, and the drift of RESET resistances after programming have been performed. Our prototype devices include PCM “pore” devices down to 20nm in actual diameter, PCM “bridge” devices down to 20nm in width, and novel “parallel cell” devices designed to trade off resistance contrast for lower resistance drift. Simple resistors integrated in series with these devices allow programming with pulses down to <10ns pulse-widths. Highly accurate current measurements can be triggered as soon as 1 millisecond after programming, so that even five-minute-long measurements can capture drift over five orders of magnitude in time. A customized finite-difference PCM simulator is capable of handling large and arbitrary 3-D structures, and can be matched against fast electrical SET and RESET experiments, slow thin-film crystallization experiments, or optical pulse experiments. Our results suggest that many of the idiosyncrasies of real PCM devices — “telegraph”-like noise, the dependence of SET resistance on pulse duration, and the variability of both repeated programming events and drift measurements even on the same device — can be traced to the important yet under-appreciated role of poly-crystalline grains and grain boundaries within the PCM device.