John Stuber

Model-based control of rapid thermal processes

Model-based control for two rapid thermal processing systems has been performed. The condition number of the process influences the control strategies selected and the quality of control that can be achieved. For the Texas Instruments RTP system, a successively linearized quadratic dynamic matrix control (QDMC) strategy using a reduced set of outputs has been developed. Experimental results of the control strategy are presented and compared with internal model control with gain scheduling. The nonlinear controller discussed shows superior performance for the test case studied. The second RTP system designed by SEMATECH exhibits improved controllability. This system has the potential for tighter control of wafer temperature using gain scheduling.<<ETX>>

Scheduling Back-End Operations in Semiconductor Manufacturing

The importance of back-end operations in semiconductor manufacturing has been growing steadily in the face of higher customer expectations and stronger competition in the industry. In order to achieve low cycle times, high throughput and high utilization while improving due-date performance, more effective tools are needed to support machine setup and lot dispatching decisions. This paper presents a new model and solution methodology aimed at maximizing the weighted throughput of lots undergoing assembly and test, while ensuring that critical lots are given priority. The problem is formulated as a mixed-integer program and solved with a reactive greedy randomized adaptive search procedure (GRASP). In phase I of the GRASP, machine-tooling combinations are tentatively fixed and lot assignments are made iteratively to arrive at a feasible solution. This process is repeated many times. In phase II, a novel neighborhood search is performed on a subset of good solutions found in phase I. Using a linear programming-Monte Carlo simulation-based algorithm, new machine-tooling combinations are identified within the neighborhood of the solutions carried over, and improvements are sought by optimizing the corresponding lot assignments. The methodology was tested on data provided by a major semiconductor manufacturer. The results show that GRASP achieves high quality solutions comparable to those obtained with CPLEX in often half the time.

Design and modeling of rapid thermal processing systems

The concept of rapid thermal processing (RTP) has many potential applications in microelectronics manufacturing, but the details of chamber design, temperature dynamics, process control, and temperature measurement remain active areas of research. This paper discusses the design rules used in an RTP test bed installed at SEMATECH with respect to the placement of lamps and the geometry and reflectivity of the enclosure. The distribution of light across the wafer was modeled, and a theory fur the wafers dynamic temperature response was derived analytically with a few simplifying assumptions, parameters for this model were estimated from experimental data to yield a set of linear ordinary differential equations with temperature dependent coefficients. This particular model form is convenient for control system design and analysis.

Daily scheduling of multi-pass lots at assembly and test facilities

In semiconductor manufacturing, wafers are grouped into lots and sent to a separate facility for assembly and test before being shipped to the customer. This paper investigates the daily scheduling of such lots in a re-entrant flow environment where it is necessary to plan for several passes of the same lot through the system. Up to a dozen operations are required during assembly and test and many are performed by the same equipment. Work in process lots that have more than a single step remaining in their route are referred to as multi-pass lots. The scheduling problem is to determine machine setups, lot assignments, and lot sequences to achieve optimal output, as measured by four objectives related to key device shortages, throughput, machine utilisation, and makespan, in that order. When more than a single pass is considered, it is not possible to develop an efficient mathematical model to represent the decision process. To find solutions, we take a multi-stage approach, first applying a reactive greedy randomised search procedure (GRASP) to develop a schedule for the current lots waiting to be processed, and then using a similar procedure to schedule additional passes and changeovers. The performance of the methodology is evaluated using data provided by a leading semiconductor manufacturer for instances with up to 36 machines, 284 tooling pieces from six families, and 1036 lots. The results indicate that, on average, multi-pass scheduling improves the weighted sum of lots processed by 40% and machine utilisation by 11% compared to the results obtained with the single-pass algorithm.

Integrating optimisation and simulation approaches for daily scheduling of assembly and test operations

The purpose of this paper is to show how the results of an optimisation model that can be integrated with the decisions made within a simulation model to schedule back-end operations in a semiconductor assembly and test facility. The problem is defined by a set of resources that includes machines and tooling, process plans for each product and the following four hierarchical objectives: minimise the weighted sum of key device shortages, maximise weighted throughput, minimise the number of machines used and minimise the makespan for a given set of lots in queue. A mixed integer programming model is purposed and first solved with a greedy randomised adaptive search procedure (GRASP). The results associated with the prescribed facility configuration are then fed to the simulation model written in AutoSched AP. However, due to the inadequacy of the options built into AutoSched, three new rules were created: the first two are designed to capture the machine set-up profiles provided by the GRASP and the third to prioritise the processing of hot lots containing key devices. The computational analysis showed that incorporating the set-up from the GRASP in dynamic operations of the simulation greatly improved its performance with respect to the four objectives.

An assignment-sequencing methodology for scheduling assembly and test operations with multi-pass requirements

This article presents a three-phase methodology for scheduling assembly and test operations for semiconductor devices. The facility in which these operations are performed is a re-entrant flow shop consisting of several dozen to several hundred machines and up to a 1000 specialized tools. The semiconductor devices are contained in lots, and each lot follows a specific route through the facility, perhaps returning to the same machine multiple times. Each step in the route is referred to as a “pass.” In the first phase of the methodology an extended assignment model is solved to simultaneously assign tooling and lots to the machines. Four prioritized objectives are considered: minimize the weighted sum of key device shortages, maximize the weighted sum of lots processed, minimize the number of machines used, and minimize the makespan. In the second phase, lots are optimally sequenced on their assigned machines using the same prioritized objectives. Due to the precedent relations induced by the pass requirements, some lots may have to be delayed or removed from the assignment model solution to ensure that no machine runs beyond the planning horizon. In the third phase, machines are reset to allow additional lots to be processed when tooling is available. The methodology was tested using data provided by the Assembly and Test facility of a leading manufacturer. The results indicate that high-quality solutions can be obtained within 1 hour when compared with those obtained with a greedy randomized adaptive search procedure. Cost reductions were observed across all objectives and averaged 62% in the aggregate.

Improving performance of dispatch rules for daily scheduling of assembly and test operations

We investigate the performance of an assembly and test semiconductor facility.New dispatch rules are developed for setting up and assigning lots to machines.The methodology combines metaheuristic logic and discrete event simulation.On-time delivery and throughput benefit greatly from the new rules. In recent years, there has been an increasing effort to improve the performance of semiconductor assembly and test facilities given their critical role in achieving on-time delivery. Using the simulation package AutoSched AP (ASAP) as the analytic tool, the goal of this paper is to show how the logic of intelligent heuristics can be combined with discrete event simulation to evaluate various dispatch rules for machine setup and scheduling in such facilities. The problem addressed is defined by a set of resources that includes machines and tooling, process plans for each product, and four hierarchical objectives: minimize the weighted sum of key device shortages, maximize weighted throughput, minimize the number of machines used, and minimize makespan for a given set of lots in queue.Three new dispatch rules are presented for configuring machines and assigning lots to them in assembly and test facilities. The first gives priority to hot lots containing key devices while using the setup frequency table obtained from our machine optimizer that takes the form of a greedy randomized adaptive search procedure (GRASP). The second embeds the more robust selection features of GRASP in the ASAP model through customization. This allows ASAP to explore a larger portion of the feasible region at each decision point by randomizing machine setups using adaptive probability distributions that are a function of solution quality. The third rule, which is a simplification of the second, always picks the setup for a particular machine that gives the greatest marginal improvement in the objective function among all candidates. The computational analysis showed that the three dispatch rules greatly improved ASAP performance with respect to the four objectives.

Characterization of Wet Batch Cleaning Process in Advanced Semiconductor Manufacturing

Wet cleaning of silicon wafers is an essential step in the fabrication of semiconductor devices. With diminishing feature and, consequently, critical particle sizes, cleaning requirements have become even more stringent. Hence, it is imperative that an understanding of the cleaning process be obtained in order to achieve the desired cleaning efficiencies. Ultrasonic and megasonic cleaning baths are the norm in advanced fabrication lines for batch cleaning of wafers. The fluid flow in these baths is quite complex and strongly influences removal of contaminant matter from the wafer surface. To better understand the effect of fluid flow on cleaning of polymeric contaminants, chemical etch experiments have been conducted using a cleaning solution on tetra-ethyl orthosilicate (TEOS) blanket wafers. The experimental results indicate a certain degree of nonuniformity and asymmetry in an otherwise symmetric system. A qualitative analysis of the observed nonuniformity has been conducted through computational fluid dynamics (CFD) simulations of the flow within the tank using a commercial CFD tool, FLUENT 6.2. An analogous heat transfer model has been set up with the CFD model, to simulate mass transfer effects resulting from the etching of the TEOS film in the experiments. A comprehensive sensitivity analysis has also been conducted within the CFD model for various parameters that might be responsible for the experimental asymmetry.

Statistics pattern analysis based virtual metrology for plasma etch processes

Virtual metrology (VM) is the prediction of end-of-batch properties (i.e., metrology data) using process variables and other information available for the process and/or the product (i.e., machine data) without physically conducting property measurement. VM (sometimes augmented with existing metrology) has been utilized in semiconductor process monitoring and control. Besides the economic benefit of replacing or reducing metrology tools, due to the instant availability of high frequency machine data, a good VM can actually provide better process monitoring and control performance compared to the same monitoring and control schemes based on the physical metrology data which often obtained at lower frequencies and usually with delays. In this paper, we propose a statistics pattern analysis (SPA) based VM approach for predicting sheet resistance using optical emission spectroscopy (OES) data. The advantageous properties of the SPA based VM are discussed. And the performance of the SPA based VM is compared with several commonly used VM algorithms in terms of prediction accuracy.

Real-time decision support for assembly and test operations in semiconductor manufacturing

This article presents an efficient procedure for prioritizing machine changeovers in a semiconductor assembly and test facility on a periodic basis. In daily planning, target machine–tooling combinations are derived based on work-in-process, due dates, and backlogs. As machines finish their current lots, they need to be reconfigured to match their target setups. The proposed algorithm is designed to achieve this objective and run in real time. It first determines which machines are set up optimally and for those that are not it sequentially calculates how best to reset them within a given amount of time taking into account when the necessary tooling will become available, the importance of the lots in queue, and the given targets. Alternatively, two mixed-integer programming models are also presented that have similar objectives. Experimental results using data provided by a leading semiconductor manufacturer indicate that high-quality solutions can be obtained with the prioritizing procedure in negligible time. In most cases, these solutions are identical to those obtained with one of the two optimization models.