John T. Pedicone

A high speed static CMOS PLA architecture

A static CMOS programmable-logic-array (PLA) architecture has been developed that enables the realization of high-speed control circuits while at the same time providing the low static power consumption inherent in CMOS technology. The PLA uses a novel circuit configuration and a two-phase clock to latch data between the AND and the OR planes. An 8-input, 13-output, 42-minterm finite state machine has been realized using an automatic generating system, in an area of 0.36 mm/sup 2/. This structure operates from near DC to above 80 MHz.<<ETX>>