John T. Stonick

A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links

In this tutorial paper, we present a general architecture for digital clock and data recovery (CDR) for high-speed binary links. The architecture is based on replacing the analog loop filter and voltage-controlled oscillator (VCO) in a typical analog phase-locked loop (PLL)-based CDR with digital components. We provide a linearized analysis of the bang-bang phase detector and CDR loop including the effects of decimation and self-noise. Additionally, we provide measured results from an implementation of the digital CDR system which are directly comparable to the linearized analysis, plus measurements of the limit cycle behavior which arises in these loops when incoming jitter is small. Finally, the relative advantages of analog and digital implementations of the CDR for high-speed binary links is considered

A multigigabit backplane transceiver core in 0.13-/spl mu/m CMOS with a power-efficient equalization architecture

A binary backplane transceiver core in 0.13-/spl mu/m dual-gate low-voltage (LV) CMOS, operating at 0.6-9.6 Gb/s with an area of 0.56 mm/sup 2/, is presented. The core uses two taps of transmit preemphasis and an adaptive receive equalization strategy incorporating one tap of unrolled decision feedback equalization (DFE), a linear equalizer, and a bandwidth control mechanism integrated with the receiver calibration circuitry. The output driver uses a cascode structure to achieve a 1.7-V peak-to-peak (p-p) differential output swing with low area and minimal overhead power. The core has extensive optional test features including a built-in bit error rate (BER) tester, voltage margining circuit, and an on-chip receiver sampling scope. The power varies from 152 to 275 mW as the speed varies from 6.25 to 9.6 Gb/s while maintaining a voltage margin of 30 mV at a BER of 10/sup -15/.

A digital clock and data recovery architecture for multi-gigabit/s binary links

In this paper we present a general architecture for digital clock and data recovery (CDR) for high speed binary links. The architecture is based on replacing the analog loop filter and VCO in a typical analog PLL-based CDR with digital components. We provide a linearized analysis of the bang-bang phase detector and CDR loop including the effects of decimation and self-noise. Finally, measured results are presented that corroborate the modeled results.

A 0.6 to 9.6Gb/s binary backplane transceiver core in 0.13/spl mu/m CMOS

A backplane transceiver core in 0.13 /spl mu/m dual-gate CMOS, operating at 0.6 to 9.6 Gb/s with an area of 0.56 mm/sup 2/ and dissipating 150 mW at 6.25 Gb/s, is presented. This core uses a unique adaptive receive equalization strategy, transmit pre-emphasis, and has extensive optional test features including a built-in BER tester and an on-chip receiver sampling scope.

A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS

A low power, small area transceiver PHY that supports PCIetrade, SATA II, and XAUI was fabricated in TSMCs 90nm dual gate CMOS. Each lane occupies an area of 400mum times 430mum. Operation also requires a clock module of 400mum times 430mum. A 4-lane, wirebond testchip consumes 195mW of power at 3.125Gb/s. The paper focuses on the analog sections of the transmit and receive blocks

F6: Signal and power integrity for SoCs

This Forum is directed toward researchers and designers working in advanced technologies over the next 3-5 years. They will be required to solve emerging issues of signal and power integrity in large, System-on-Chip applications which will raise issues of increasing difficulty. While struggling for higher performance, the designer must battle escalating noise and cross-talk. Interconnect delay and coupling will require new methods of routing and signal transmission. Supply-grid design will take increasing account of limited package and chip metalization through independent power domains, active and passive supply-noise cancellation, and voltage scaling. Increasingly- sensitive analog and RF circuit blocks must counter digital chip noise. Stringent clock-jitter and skew targets, and power-dissipation limitations will be addressed by independent clock domains, resonant clocking, and frequency scaling.

10–40 Gb/s I/O design for data communications

The importance of I/O data rates beyond 10Gb/s is growing rapidly. Supporting these data rates introduces new challenges beyond those faced at lower data rates. The objective of this forum is to present both electrical and optical I/O approaches to meeting these challenges at the architecture and circuit levels. This forum commences with two talks offering an overview of circuits and systems issues in CMOS technology. They are followed by two presentations focusing on the challenges of 20Gb/s+ over electrical backplanes and very lossy electrical channels. The next talk compares conventional analog equalization versus digital (data converter based) approaches from a system perspective. The final two talks focus on optical solutions, highlighting the relative strengths and weaknesses of electrical and optical approaches. The forum concludes with a panel discussion providing the opportunity for participants to give feedback and ask questions. The forum is aimed at circuit designers and engineers working on high-speed wireline transceivers.

Optical PCB interconnects, Niche or mainstream?

Summary form only given. The continued scaling of information processing systems-on-a-chip using modern technology have made conventional electrical interconnects using copper the bottleneck for data traffic in many applications. Efforts in the area of optical backplane and technology have been underway for several years, generating significant interest due to its potential benefits in power, density and speed. Recently, these efforts have led to discussions regarding the role of embedded optics for chip to chip communication on printed circuit boards. Most signficantly, the advancement in silicon photonics compatible to CMOS technology have accelerated this discussion. A consensus appears to be emerging that PCB interconnects for mainframes and high-end servers will leverage optical technologies, but will these approaches ever go mainstream?

F6: High-speed transceivers: Standards, challenges, and future

Multi-Gbps transceivers have evolved from what were once exotic special-purpose cells to ubiquitous building blocks that are expected to function as the glue bet ween critical compute, communications, and storage elements. As such they are expected to function flawlessly, interoperate cleanly, and consume little power, area, and system design mindshare. As part of the commoditizing of transceivers, the pressure to achieve multiple standards compliance from individual designs has increased dramatically no longer are ASIC or system designers content with a single PHY for a single standard. The consequential impact on the design space means link designers must often right size a swiss-army-knife design including power and area optimization; you dont want too many or too few blades. Sometimes conflicting standards requirements can make customization and optimization a real challenge in this space. Jared Zerbe of Rambus will review some of the fundamental transceiver challenges and techniques used to address them, including a discussion of the impact of multi-standard compliance on the transceiver design effort and ultimate performance. Following this, Thomas Toifl of IBM will discuss the design challenges and solutions to data rates above 20Gb/s. Main challenges are achieving the required bandwidth with full ESD protection, the DFE loop timing, and overall design complexity. Marcus van lerssel of Snowbush IP will discuss implementation challenges and the benefits of a multi-standard PHY supporting Ethernet/PCIe/SATA/USB. Takeshi Horiefrom Fujitsu will present Ethernet standards and the technologies required to realize 10GB serial backplane transfer for 10GB Ethernet. When it comes to buidling standards compliant PHYs, IP providers face challenges that arise from the need to proliferate the design across many process geome tries/foundries and also from the large variability in customers expertise in package design and signal integrity analysis. Dan Weinlader of Synopsys will discuss how standards influence these challenges. The main focus of standards over the last few years has understandably been on addressing the bandwidth curve. The need to address the rising power struggle of SoCs is usually recognized, but limited to simple power targets. The final two presentations in this forum will focus on energy efficiency by Fulvio Spagna of Intel and on low-power solutions by Anthony Sanders of Lantiq.

F5: ATAC: High-speed interfaces

The goal of this Forum is to provide circuit designers with an opportunity to learn from leading experts about the design issues and system-level challenges that arise in the development of transceivers for a wide cross-section of application areas and associated standards. The transceivers for these different standards share some similarities but also marked differences. The audience will have an opportunity not only to learn about these similarities and differences, but also to develop an understanding as to how they arose and why they exist. Additionally, the audience will be able to garner insight into where these standards are heading, and what challenges lie ahead, in the future.