John Y. Oliver

Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor

We present Synchroscalar, a tile-based architecture for embedded processing that is designed to provide the flexibility of DSPs while approaching the power efficiency of ASICs. We achieve this goal by providing high parallelism and voltage scaling while minimizing control and communication costs. Specifically, Synchroscalar uses columns of processor tiles organized into statically-assigned frequency-voltage domains to minimize power consumption. Furthermore, while columns use SIMD control to minimize overhead, data-dependent computations can be supported by extremely flexible statically-scheduled communication between columns. We provide a detailed evaluation of Synchroscalar including SPICE simulation, wire and device models, synthesis of key components, cycle-level simulation, and compiler- and hand-optimized signal processing applications. We find that the goal of meeting, not exceeding, performance targets with data-parallel applications leads to designs that depart significantly from our intuitions derived from general-purpose microprocessor design. In particular, synchronous design and substantial global interconnect are desirable in the low-frequency, low-power domain. This global interconnect supports parallelization and reduces processor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Overall, Synchroscalar provides programmability while achieving power efficiencies within 8-30/spl times/ of known ASIC implementations, which is 10-60/spl times/ better than conventional DSPs. In addition, frequency-voltage scaling in Synchroscalar provides between 3-32% power savings in our application suite.

Smartphone Evolution and Reuse: Establishing a More Sustainable Model

The dark side of Moores Law is our societys insatiable need to constantly upgrade our computing devices. The high cost in manufacturing energy, materials and disposal is more worrisome the increasing number of smartphones. Repurposing smartphones for educational purpose is a promising idea and shown success in recent years. Our previous work has shown that although different components in smartphones degrade from use, their functionalities, available resources and power supplies are still able to satisfy the requirement of educational applications. In this study, we demonstrate the potential benefits of reusing smartphones by analyzing their manufacturing and life-time energy. The key challenge is the design of software that can adapt to extreme heterogeneity of devices. We also characterize different types of heterogeneities among different generations of smartphones from HTC and Apple, including processing capability, storage resource and various features. We propose insights to aid establishing a sustainable model of designing mobile applications for phone reuse.

Tile size selection for low-power tile-based architectures

In this paper, we investigate the power implications of tile size selection for tile-based processors. We refer to this investigation as a tile granularity study. This is accomplished by distilling the architectural cost of tiles with different computational widths into a system metric we call the Granularity Indicator (GI). The GI is then compared against the communications exposed when algorithms are partitioned across multiple tiles. Through this comparison, the tile granularity that best fits a given set of algorithms can be determined, reducing the system power for that set of algorithms. When the GI analysis is applied to the Synchroscalar tile architecture[1], we find that Synchroscalars already low power consumption can be further reduced by 14% when customized for execution of the 802.11a reciever. In addition, the GI can also be a used to evaluate tile size when considering multiple applications simultaneously, providing a convenient platform for hardware-software co-design.

Credit-based dynamic reliability management using online wearout detection

As circuit geometries continue to shrink, and supply voltages remain relatively constant, circuit wearout becomes a concern. We propose that the relative reliability of the circuits of a processor be exposed to the operating system, and be managed by a credit-based wearout monitor. This wearout monitor receives dynamic updates of the reliability of circuits through the use of stability detector circuits that are small enough to be widely deployed. We find that through the combined use of the wearout monitor and stability detectors, we can efficiently and accurately manage the reliability of a processor, and re-coup the performance of a processor that would otherwise be lost when processors are over-provisioned to meet an expected lifetime. We simulate a 16 core DSP with a wearout monitor and stability detectors on a mix of four different media algorithms. Using the wearout monitor and stability detectors, we find that by reducing average performance by only 5%, we can increase the lifetime of the processor by 46%.

Efficient orchestration of sub-word parallelism in media processors

Communication and multimedia applications with increased data rates and enhanced functionality continuously raise the bar for the computational requirements of future microprocessors. In order to meet these computational demands it is necessary to exploit sub-word parallelism efficiently. We propose to make sub-word data movement a first-class operation in microprocessor architectures by introducing a Sub-word Permutation Unit (SPU)in the execution pipeline. The SPU is evaluated in the context of the MMX media co-processor for the Intel Pentium architectures, but our results can be extended to any processor that supports sub-word parallelism. We find that the SPU all ws us to orchestrate sub-word data placement prior to computation, thus all wing the MMX functional units to concentrate on performing calculations. Furthermore, we introduce a decoupled SPU control mechanism at the basic block level which allows static optimization to eliminate data-movement verhead in tight loops, where most media and signal processing occurs. We demonstrated that anywhere from 4% to 20% improvement can be obtained on key media and signal processing kernels with as little as 1% increase in hardware resources.

A case for smartphone reuse to augment elementary school education

The rapid growth of information technology has led to substantial economic and societal benefits. Unfortunately, rapid improvements in technology has also led to an unsustainable “disposable” model in which devices are replaced in a matter of months. This model is especially problematic in the cell phone area, where over a billion phones are manufactured per year.

Improving DSP Performance with a Small Amount of Field Programmable Logic

We show a systematic methodology to create DSP + field-programmable logic hybrid architectures by viewing it as a hardware/software codesign problem. This enables an embedded processor architect to evaluate the trade-offs in the increase in die area due to the field programmable logic and the resultant improvement in performance or code size. We demonstrate our methodology with the implementation of a Viterbi decoder. A key result of the paper is that the addition of a field-programmable data alignment unit (FPDAU) between the register-file and the computational blocks provides 15%-22% improvement in the performance of a Viterbi decoder on the state-of-the-art TigerSHARC DSP. The area overhead of the FPDAU is small relative to the DSP die size and does not require any changes to the programming model or the instruction set architecture.

A semi-autonomous embedded systems course

Educational research has shown that students learn with deeper understanding and retain that understanding for a greater duration when they learn in an environment of inquiry. In order to foster an environment of inquiry in an embedded systems course, we have redesigned the course to give students more and more autonomy with course material as the course progresses. In this paper, we describe the design and preliminary assessment of a semi-autonomous embedded systems course in the computer engineering program at Cal Poly, San Luis Obispo. Preliminary assessment data indicate that the course appears to provide an environment of inquiry for students, but further assessment is required to determine if the semi-autonomous nature of the course increased student understanding and retention of course material.

Synchroscalar: initial lessons in power-aware design of a tile-based embedded architecture

Embedded devices have hard performance targets and severe power and area constraints that depart significantly from our design intuitions derived from general-purpose microprocessor design. This paper describes our initial experiences in designing Synchroscalar, a tile-based embedded architecture targeted for multi-rate signal processing applications. We present a preliminary design of the Synchroscalar architecture and some design space exploration in the context of important signal processing kernels. In particular, we find that synchronous design and substantial global interconnect are desirable in the low-frequency, low-power domain. This global interconnect enables parallelization and reduces processor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Furthermore, statically-scheduled communication and SIMD computation keep control overheads low and energy efficiency high.

Work in progress: Outreach assessment: Measuring engagement: An integrated approach for learning

The Learn By Doing Lab (LBDL) at Cal Poly, San Luis Obispo is an on-campus laboratory where 5th through 8th grade students are taught by undergraduates who may be planning a careers in teaching. The two populations -elementary students and undergraduates - are equally important in the process. Since 2008, the lab has seen over 4000 elementary and junior high students and over 100 undergrads have participated. In most outreach assessment the number of individuals participating is an important metric, but this last Spring we experimented with a more in depth measure of effectiveness. As in any learning experience engagement in the process is an essential ingredient. Although there are several methods of measuring engagement, we chose to observe the activity of the participants as a proxy for engagement. Two industrial engineering (IE) undergraduates who themselves have been exposed to the topics of work sampling and observation studies had an opportunity to improve professional skills through this application. This involvement of undergraduates is consistent with the LBDL and Cal Polys motto of “learn by doing.” These two students, who are also coauthors, spent multiple hours coding and randomly sampling the of the elementary and junior high students as well as the undergraduate teachers activities. Not only did the IE students discover important insights for the LDBL they also learned how to apply work sampling in a research setting. This paper discusses the integrated learning environment and the next steps involved in these undertakings.