Johnny Öberg

A network on chip architecture and design methodology

We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m/spl times/n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical- and architectural-level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (IP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multi-processors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.

Lowering power consumption in clock by using globally asynchronous locally synchronous design style

Power consumption in clock of large high performance VLSIs can be reduced by adopting globally asynchronous, locally synchronous design style (GALS). GALS has small overheads for the global asynchronous communication and local clock generation. We propose methods to (a) evaluate the benefits of GALS and account for its overheads, which can be used as the basis for partitioning the system into optimal number/size of synchronous blocks, and (b) automate the synthesis of the global asynchronous communication. Three realistic ASICs, ranging in complexity from 1 to 3 million gates, were used to evaluate GALS benefits and overheads. The results show an average power saving of about 70% in clock with negligible overheads.

Load Distribution with the Proximity Congestion Awareness in a Network on Chip

In networks on chip (NoC) very low cost and high performance switches are of critical importance. For a regular two-dimensional NoC, we propose a very simple, memoryless switch. In the case of congestion, packets are emitted in a non-ideal direction, also called deflective routing. To increase the maximum tolerable load of the network, we propose a proximity congestion awareness (PCA) technique, where switches use the load information of neighbouring switches, called stress values, for their own switching decisions, thus avoiding congested areas. We present simulation results with random traffic which show that the PCA technique can increase the maximum traffic load by a factor of over 20.

A case study on hardware/software partitioning

We present an analysis of a fully automatic method to accelerate standard software in C or C++ by use of field programmable gate arrays. Traditional compiler techniques are applied to the hardware/software partitioning problem and a compiler is linked to state of the art hardware synthesis tools. Time critical regions are identified by means of profiling and are automatically implemented in user programmable logic with high level and logic synthesis design tools. The underlying architecture is an add-on board with user programmable logic connected to a Spare based workstation via the system bus. We present an analysis and case study of this method. Eight programs are used as test cases and the data collected by applying this method to programs is used to discuss potentials and limitations of this and similar methods. We discuss architectural parameters, programming language properties, and analysis techniques.<<ETX>>

Grammar-based hardware synthesis of data communication protocols

For a synthesis methodology to support implementation independent design specification, a capability for design space exploration is essential. In this paper we present such a methodology for a specific domain: data communication protocols. A natural way to specify various elements of protocols is in terms of a grammar annotated with actions. Our language for protocol specification, called PRO-GRAM, is based on this idea. The hardware specification of the protocol is done by specifying the bit-patterns of the tokens the protocol is supposed to parse together with the actual grammar to parse the input stream. By specifying constraints on the input and output stream ports, the designer is allowed to explore alternative realisations with different widths of the I/O ports. The PRO-GRAM compiler outputs VHDL-code suitable for logic synthesis.

Globally asynchronous locally synchronous architecture for large high-performance ASICs

Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a realistic design done in 0.25 micron, ranging in operating frequencies from 20 MHz to 1 GHz. The results show that the net power savings compared to fully synchronous designs are on an average about 30%.

Toward a scalable test methodology for 2D-mesh Network-on-Chips

This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the NoC are tested with BIST, running at full clock-speed, and in a functional-like mode. The BIST is carried out as a go/no-go BIST operation at start up, or on command. It is shown that the proposed methodology can be applied for different implementations of deflecting switches, and that the test time is limited to a few thousand-clock cycles with fault coverage close to 100%

Grammar-based hardware synthesis from port-size independent specifications

A protocol defines how systems communicate. There are two ways of specifying the protocol, the language of communication. One way is to specify the automaton that recognizes the language, and this is the approach taken by SDL, etc. The other more abstract way ss to specify the grammar of the language and let a tool synthesize the automaton. Directly specifying the automaton makes the specification implementation dependent in two ways: the time behavior is specified in terms of states, and the width of the inputs and outputs is fixed. By specifying the grammar, the specification is potentially independent of both these implementation details and allows design space exploration in these dimensions. This paper presents a grammar-based language, called Program, that supports a port-size independent specifications methodology and its application to parts of the Operation and Maintenance protocol, a typical application from the ATM world. The methodology has also been applied to another test set of example designs and compared to standard RTL synthesis and HLS in order to evaluate the quality of the produced designs.

System Level Virtual Prototyping of DSP SOCs Using Grammar Based Approach

As we move from algorithm on a chip to system on a chip era, the design bottleneck is shifting from individual DSP functions to global control that composes a system from these functions. The practice in industry suffers from global control entering the design flow too late, discontinuity between functional modeling and implementation phase and mixing data flow with global control. MASIC—Maths to ASIC—is a methodology proposed in this paper that targets DSP SOCs and addresses these issues. Global control is specified in a grammar notation and integrates the output of functional modeling phase, the DSP functions, by referencing them. A virtual prototype is automatically built from such a specification that models the global control in VHDL and cosimulates with the DSP functions in C from the functional modeling phase. A highly efficient verification methodology based on separating the verification of global control from DSP functions is proposed. A smooth path to cycle true implementation is possible using either behavioral synthesis, IPs for the DSP functions or manual implementation. Experiments using realistic examples like GSM base band processing, rake receiver and some smaller examples have been carried out to quantify the benefits of MASIC.

Grammar based modelling and synthesis of device drivers and bus interfaces

ProGram, a grammar-based communication protocol description language, is used for architectural independent modelling of device drivers and bus interfaces for mixed hardware/software systems. The specification of the protocol is separated from the description of processor bus interfaces and operating system device driver interfaces, which ensures a high efficiency in device driver development and maintenance. A synthesis method for device drivers is presented, together with results on modelling and implementation efficiency for both device drivers and bus interfaces.