Joji Philip

A fault modeling technique to test memory BIST algorithms

The amount of memory being embedded on chip is growing rapidly. This strongly implies that memory built-in-self-test (BIST) logic assumes utmost importance amongst all on chip self test logic. Therefore the BIST logic should be comprehensively validated before fabrication. The key to this achievement lies in a robust memory fault model. In this paper we propose a novel fault modeling technique. This technique can scale to emulate any kind of memory architecture currently in use. The memory architecture and the location of any fault that can occur in the cell array are represented in terms of equations. The technique applies these equations and calculates an address where the fault can be modeled.

ULTRA HIGH SPEED PACKET BUFFERING USING "PARALLEL PACKET BUFFER"

Modern switches and routers often use dynamic RAM (DRAM) in order to provide large buffer storage space. However, the effective bandwidth of DRAM is frequently a limiting factor in the design of high-speed switches and routers. The focus of this paper is to introduce a packet-buffering architecture called the parallel packet buffering (PPB), which increases the effective memory bandwidth significantly. PPB incorporates n cheaper, narrower and smaller DRAM modules to emulate a common memory buffer. An efficient read/write scheme and memory selection policy ensures the optimum usage of all the memory modules. PPB is particularly useful for extremely high-speed packet buffering applications. We will show that, for most of the traffic profiles, the architecture utilizes the total buffering space much more efficiently than other architectures for high speed packet buffering. In addition, our simulation results show that the PPB architecture achieves much higher bandwidth than a single memory with same aggregate data-width for any traffic.