Jon Beecroft

QSNET/sup II/: defining high-performance network design

QSNET/sup II/ optimizes interprocessor communication in systems built from standard server building blocks. Its short-message processing unit permits fast injection of small messages, providing ultra-low latency and scalability to thousands of nodes. Thus, in a sense, the high-performance network in a cluster computer is the computer because it largely defines achievable performance, widening the range of the applications a cluster can efficiently execute, as well as defining its scalability, fault tolerance, system software, and overall usability.

Meiko CS-2 interconnect Elan-Elite design

Abstract The architecture of the interprocessor communications subsystem in the Meiko CS-2 MPP is discussed. This utilises a ‘fat tree’ network constructed from high performance crosspoint switches. Processing Elements interface to this network via a communications co-processor which contains intelligence to handle virtual addressing and ensures very low message start up times. Measured performance figures are given for the system running a variety of different programming models.