Jonas Berg

Can molecular resonant tunneling diodes be used for local refresh of DRAM memory cells

The requirements of resonant tunneling diodes (RTDs) in general and molecular diodes in particular for use as local refresh in low-power DRAM memory cells are discussed. Simulations show that none of the so far published molecules showing negative diAerential resistance have adequate electrical properties. Further, simulations show that present RTDs in III‐V materials or SiGe are not compatible with the demands of future DRAM generations. A detailed list of requirements on the electrical properties of molecular RTDs or RTDs made of nanocrystals is presented. For instance, the valley current of the RTDs should be in the 10 ˇ16 A range. The issues of acceptable diAerences in the number of active molecules constituting the two RTDs, and the maximum acceptable contact resistance between the molecules and the silicon substrate are addressed. ” 2000 Elsevier Science Ltd. All rights reserved.

Electrical properties of Si?SiO2?Si nanogaps

The chances of attaching organic molecules to silicon surfaces can be considerably enhanced if a robust nanogap structure with silicon electrodes can be used to connect the molecules. We describe the electrical properties of such an electrode structure, with a separation of the silicon surfaces in the 3-7 nm range. These silicon nanogaps are manufactured by partly removing the silicon dioxide insulator from a silicon-oxide-silicon material stack, by using a selective oxide etchant. After the activation of the gap (the etching), current instabilities appear, which are comparable to the properties of thin oxides after soft breakdown. Applying a constant voltage can reduce these current instabilities. We also address the issue of surface leakage currents for these nanogap structures.

Compatibility assessment of CVD growth of carbon nanofibers on bulk CMOS devices.

We compare the level of deterioration in the basic functionality of individual transistors on ASIC chips fabricated in standard 130 nm bulk CMOS technology when subjected to three disparate CVD techniques with relatively low processing temperature to grow carbon nanostructures. We report that the growth technique with the lowest temperature has the least impact on the transistor behavior.

Nanoimprint lithography using vertically aligned carbon nanostructures as stamps

Nanoimprint lithography using vertically aligned carbon nanostructures as stamps is reported. The functionality of the stamp is demonstrated through lift-off and etch-back processes after pattern replication. The imprint process is robust and the stamp structures survived more than 50 consecutive imprints. In this paper we demonstrate this for feature sizes ranging from 80 nm to 200 microm where the aspect ratio of the individual nanostructures surpasses 1:5 with a pitch down to 100 nm. This demonstration opens up the possibility of utilizing vertically grown carbon nanostructures for manufacturing extremely high aspect ratio and small pitch stamps for nanoimprint lithography.

Carbon Nanofibers (CNF) for enhanced solder-based nano-scale integration and on-chip interconnect solutions

While the density of chip-to-chip and chip-to-package component interconnections increases and their size decreases the ease of manufacture and the interconnection reliability are being dangerously reduced. This paper introduces the use of Carbon Nanofibers (CNF) grown on chip as an embedded reinforcing material for nano-solder interconnections and as bonding material (adhesive) for chip-to-package solutions. Interconnections are realized by means of microbumps which can be less than 10 um in diameter and up to 20 um high. Such micro-bumps are shown to be solderable using conventional thermal-compression and micro-bumps. Using CNF embedded in polymer is shown to provide a robust solution for chip-to-package interconnections.

A silicon structure for electrical characterisation of nanoscale elements

The problem of mass manufacturing electrode structures suitable for contacting nanoscale elements lies primarily in the difficulty of fabricating a nanometre-scale gap between two electrodes in a well controlled, highly parallel manner. In ULSI circuit production, the gate and substrate in MOSFETs are routinely fabricated with a precise vertical spacing of 3 nm between them. In this work, we have investigated a number of highly parallel methods for the generation of nanogaps, including reconfiguration of the ubiquitous MOS device structure. The silicon dioxide layer that provides vertical separation and electrical insulation between two regions of silicon (the crystalline substrate and the poly-crystalline gate) gives a leakage current of 1 nA P -2 at 1 V for an oxide thickness of 2 nm [1]. This will enable objects the size of single molecules that are held across this layer to be detected electrically if they provide currents on the nanoampere scale, assuming a parasitic area for leakage between gate and substrate of order 1 µm 2 . In the future this kind of device has the potential to provide a bolt-on technology for the fabrication of ULSI circuits in which conventional CMOS devices are directly hybridised with functional nanoscale elements.

A Study on Integration of Molecular Devices into CMOS Compatible Technology

One main obstacle for measuring matter at the level of single molecule is the technology to make a bridge between molecules and microscopic structures (electrodes). A method of fabricating vertical silicon based nanogaps for contacting nanoscale elements has been developed and exploited to confront this problem. The developed technique is compatible to existing CMOS fabrication technology, reproducible and the gap size is easy to measure by simple capacitance measurements. Chemical treatment to attach any kind of nanoscale elements into the nanogap is an important issue. In this paper, we address problems related to surface leakage induced from different chemical processes. We have studied the effects of solvents on the surface leakage as well as surface leakage induced by nano components themselves. Surface leakage is a diffusion current process, and a set of parameters describing it has been used to compare the influence from different chemical processes. The study on solvents confirmed no predominant surface leakage induced by the presence of solvents like toluene and chloroform.

Low frequency noise in silicon nanogaps

Silicon nanogaps are contact structures for connecting organic molecules. An insulating layer is removed by etching, and this dramatically increases the current levels and the noise, which closely resembles a 1/f-law and scales with the square of the current. After etching the noise level at 30 Hz and 10 nA is in the order of 10-21 A2/Hz, which is more than two orders of magnitude larger than before etching. We model the noisy behavior by several percolation paths in parallel at the etched surface between the electrodes, and compare with soft breakdown in thin oxide.

High frequency properties of silicon-on-insulator and novel depleted silicon materials

Abstract High frequency properties of substrates such as substrate losses and cross-talk were investigated for silicon-on-insulator (SOI) materials and for a novel depleted silicon material. Simulations were made to reveal high frequency properties of SOI MOSFETs made on fully depleted SOI materials of different substrate resistivities. The substrate resistivity was varied from 0.01 Ω cm to 10 k Ω cm . It was found that the high frequency properties of intrinsic transistors were independent of the substrate resistivity, but a system consisting of both active and passive components showed reduced cut-off frequency, f T , and maximum oscillation frequency, f max , for low substrate resistivities. The obtained information on the importance of the silicon substrate resistivity has been used to manufacture a depleted silicon material by use of wafer bonding. The novel material is intended as substrate for high frequency applications. The space charge regions surrounding a bonded silicon/silicon interface deplete the silicon thereby reducing substrate losses at high frequencies. The novel material has been characterised electrically for frequencies up to 40 GHz using metal transmission lines and cross-talk structures on its surface. The measurements have been compared to similar measurements on bulk silicon, SIMOX and quartz substrates. The depleted region of the novel material shows up in its electrical characteristics.

Analysis of the Use of Molecular Resonant Tunneling Diodes for Local Refresh of Dynamic Random Access Memory Cells

Simulations have been made to analyze the use of molecular resonant tunneling diodes for local refresh of DRAM (Dynamic Random Access Memory) cells. Local refresh can be provided by a latch consisting of a pair of resonant tunneling diodes connected to the storage capacitor of the cell. Such a solution would significantly reduce the standby power consumption of the DRAM cell. We have compared the requirements on the resonant tunneling diodes for proper refresh operation with the electrical properties of published molecules with resonant IV-curves. The simulations show that no molecules with resonant electrical properties published so far in the literature have properties making them useful for this particular application. This is true also for low temperature operation. The issues of maximum tolerable series resistance and of maximum tolerable fluctuations in the number of attached molecules have also been addressed. Our results show that the focus for development of molecules with resonant electrical properties should be to find molecules with resonance for lower applied voltages and lower current levels than the molecules published so far. If the synthesis of new molecules with attractive properties is successful the merging of silicon technology and molecular electronics, for instance for new generations of DRAM cells, is a realistic future path of microelectronics.