Jonathan A. Clarke

Fast word-level power models for synthesis of FPGA-based arithmetic

This paper presents power models for multiplication and addition components on FPGAs which can be used at a high-level design description stage to estimate their logic and intra-component routing power consumption. The models presented are parameterized by the word-length of the component and the word-level statistics of its input signals. A key feature of these power models is the ability to handle both zero mean and non-zero mean signals. A method for measuring intra-component routing power consumption is presented, enabling the power models to account for both logic and routing power in components. The resulting models are equations which can be used to estimate the power consumed in an arithmetic component in a fraction of a second at the pre-placement stage of the design flow. The models have a mean relative error of 7.2% compared to bit-level power simulation of the placed-and-routed design

Parameterized logic power consumption models for FPGA-based arithmetic

The need for fast power estimation methods is a growing requirement in tools which perform power consumption optimization. This paper addresses the requirement by presenting a technique which is capable of providing a power estimate using only the word-level statistics of signals within an arithmetic hardware design. By abstracting away from the low-level details of a design it is possible to reduce the time required to calculate the power consumption dramatically. Power models for multiplication and addition have been constructed using an experimental method, and the operation of these models is illustrated by estimating the power consumed in logic for two example circuits: a sum of products and a parameterised polynomial evaluation. The proposed method is capable of providing an estimate within 10% of low-level power estimates given by XPower.

Word-length selection for power minimization via nonlinear optimization

This article describes the first method for minimizing the dynamic power consumption of a Digital Signal Processing (DSP) algorithm implemented on reconfigurable hardware via word-length optimization. Fast models for estimating the power consumption of the arithmetic components and the routing power of these algorithm implementations are used within a constrained nonlinear optimization formulation that solves a relaxed version of word-length optimization. Tight lower and upper bounds on the cost of the integer word-length problem can be obtained using the proposed solution, with typical upper bounds being 2.9% and 5.1% larger than the lower bounds for area and power consumption, respectively. Heuristics can then use the upper bound as a starting point from which to get even closer to the known lower bound. Results show that power consumption can be improved by up to 40% compared to that achieved when using simple word-length selection techniques, and further comparisons are made between the minimization of different cost functions that give insight into the advantages offered by multiple word-length optimization.

PowerBit - power aware arithmetic bit-width optimization

In this paper we present a novel method reducing the dynamic power consumption in FPGA-based arithmetic circuits by optimizing the bit-widths of the signals inside the circuit. The proposed method is implemented in the tool PowerBit, which makes use of macro models parameterized by word-level signal statistics to estimate the circuit power consumption during the optimization process. The power models used take in to account the generation and propagation of signal glitches through the circuit. The bit-width optimization uses a static analysis technique which is capable of providing guaranteed accuracy in the design outputs. We show that, for sample designs implemented on FPGAs that improvements of over 10% are possible for multiple bit-width allocated designs optimized for power compared to designs allocated uniform bit-widths

Modeling of glitch effects in FPGA based arithmetic circuits

One of the requirements when using high-level power optimization techniques is the ability to estimate circuit power consumption quickly. Bit-level estimation techniques which take into account the glitch activity in a circuit take too long to provide power estimates. In this paper we present a novel method which can provide fast estimates for the logic and intra-routing power consumption in digital circuits whilst taking into account the glitch activity but relying purely on the word-level statistics of the signals. The proposed method models the propagation of glitch activity in signals through the arithmetic components in circuits, and using this information estimates the logic and intra-routing power consumption. For arithmetic circuits implemented on FPGAs we demonstrate that previous macro-model based power estimation techniques consistently under-estimate the power consumption by up to 20 times, whilst this work can provide estimates to within a mean relative error of 30% compared to low-level power estimation

On the Feasibility of Early Routing Capacitance Estimation for FPGAs

Knowing the capacitance of circuit nets in an FPGA design is essential when computing the dynamic power consumed by switching these nets. Before a circuit is placed, however, there is little information available to allow the capacitance of routing wires to be estimated. In this paper we study the feasibility of estimating routing capacitance before RTL-synthesis to allow high-level power consumption optimization algorithms to be able to target routing power. We propose a novel method for estimating the capacitance of nets before RTL-synthesis and show that this method improves the accuracy and the rank ordering of the net-by-net estimates made over existing fan-out based techniques.

High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic

The PhD project described in this paper aims to use word-length optimization techniques to automatically optimize the dynamic power consumption of high-level descriptions of DSP algorithms intended for implementation on FPGA, before or during synthesis. By developing models which can quickly estimate the power consumed by a system from a high-level description of the algorithm it implements, the authors work allow for existing word-length optimization techniques to minimize the power consumption of a system, subject to acceptable signal distortion constraints

Health systems should be publicly funded and publicly provided

A market in healthcare increases the likelihood of inequity and exploitation, with suboptimal care for both rich and poor, say Neena Modi and colleagues

Glitch-aware output switching activity from word-level statistics

This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures of the correlation and variance of the input signals to these components. This will allow the power consumed in the output wires of these components to be estimated from a high-level description before RTL-synthesis, without resorting to time-consuming low-level simulation. The proposed model combines knowledge of the internal construction of adders on FPGAs with the Transition Density model for activity propagation [1] and typical activity profiles for signals within Digital Signal Processing (DSP) systems according to the DBT model [2], and is characterized using device-level power measurements. The resulting closed form expression allows power consumption estimates to be quickly made in order to drive design exploration decisions during power-aware synthesis. The model has been verified by comparing it to power estimates generated by the low-level power estimation tool XPower, achieving a mean relative error in total activity of 2.1%, whilst being several orders of magnitude times faster than XPower.

Paediatric weight estimation by age in the digital era: optimising a necessary evil

BACKGROUND Age-based weight estimation methods are regularly used in paediatric emergency medicine despite their well-established inaccuracy. AIM Determine the potential improvement in accuracy achievable by the use of a new mobile application, based on CDC/WHO weight-for-age centile data, which incorporates a gender assignment, a body habitus assessment, and which is capable of an age-in-months based calculation. METHODS A theoretical, simulated validation study, comparing the performance of the widely used APLS/EPALS formulae against two contemporary habitus-adjusted methods, and the Helix Weight Estimation Tool. 1,070,743 children from the 2015/2016 UK National Child Measurement Program dataset, aged between 4 and 5 and 11 and 12 years, had age-based weight estimates made by all five methods. RESULTS Primary outcomes were the percentage of weight estimations within 10%, 20%, and those greater than 20% discrepant from actual weight for each method. Our theoretical, gender-dependent, habitus-adjusted method performed better than all other methods across all error thresholds. The overall number of estimations within 10% was 70.4%, and within 20% was 95.45%. The mean percentage error was -1% compared to actual weight. CONCLUSION The use of a digital tool incorporating a subjective assessment of body habitus, gender assignment, and the ability to estimate weight based on age-in-months might be able optimise the process of paediatric weight estimation by age, making this practice as safe and accurate as possible for the occasions when weight estimation by age is chosen over length-based methods.