Jonathan Lin

CMOS EEPROM cell with tunneling window in the read path

CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors

Control gate-addressed CMOS non-volatile cell that programs through gates of CMOS transistors

CMOS memory cell with gate oxide of both NMOS and PMOS transistors as tunneling window for program and erase

Non-volatile memory cells using only positive charge to store data

Field implant for semiconductor device

Low power CMOS array for a PLD with program and erase using controlled avalanche injection

Completely complementary MOS memory cell with tunneling through the NMOS and PMOS transistors during program and erase

Memory cell for a programmable logic device (PLD) avoiding pumping programming voltage above an NMOS threshold

Use of borophosphorous tetraethyl orthosilicate (BPTEOS) to improve isolation in a transistor array