Jonathan Piat

An open framework for rapid prototyping of signal processing applications

Embedded real-time applications in communication systems have significant timing constraints, thus requiring multiple computation units. Manually exploring the potential parallelism of an application deployed on multicore architectures is greatly time-consuming. This paper presents an open-source Eclipse-based framework which aims to facilitate the exploration and development processes in this context. The framework includes a generic graph editor (Graphiti), a graph transformation library (SDF4J) and an automatic mapper/scheduler tool with simulation and code generation capabilities (PREESM). The input of the framework is composed of a scenario description and two graphs, one graph describes an algorithm and the second graph describes an architecture. The rapid prototyping results of a 3GPP Long-Term Evolution (LTE) algorithm on a multicore digital signal processor illustrate both the features and the capabilities of this framework.

3GPP Long Term Evolution

Terrestrial mobile telecommunications started in the early 1980s using various analog systems developed in Japan and Europe. The Global System for Mobile communications (GSM) digital standard was subsequently developed by the European Telecommunications Standards Institute (ETSI) in the early 1990s. Available in 219 countries, GSM belongs to the second generation mobile phone system. It can provide an international mobility to its users by using inter-operator roaming. The success of GSM promoted the creation of the Third Generation Partnership Project (3GPP), a standard-developing organization dedicated to supporting GSM evolution and creating new telecommunication standards, in particular a Third Generation Telecommunication System (3G). The current members of 3GPP are ETSI (Europe), ATIS(USA), ARIB (Japan), TTC (Japan), CCSA (China) and TTA (Korea). In 2010, there are 1.3 million 2G and 3G base stations around the world and the number of GSM users surpasses 3.5 billion.

Interface-based hierarchy for synchronous data-flow graphs

Dataflow has proven to be an attractive computation model for programming digital signal processing (DSP) applications. A restricted version of dataflow, termed synchronous dataflow (SDF), offers strong compile-time predictability properties, but has limited expressive power. In this paper we propose a new type of hierarchy in the SDF domain allowing more expressivity while maintaining its predictability. This new hierarchy semantic is based on interfaces that fix the number of tokens consumed/produced by a hierarchical vertex in a manner that is independent or separate from the specified internal dataflow structure of the encapsulated subsystem. This interface-based hierarchy gives the application designer more flexibility in iterative construction of hierarchical representations, and experimentation with different optimization choices at different levels of the design hierarchy.

FPGA based accelerator for visual features detection

In the context of obstacle detection and tracking for a vision-based ADAS (Advanced Driver Assistance System), one mandatory task is vehicle localization. Vision-based SLAM (Simultaneous Localization and Mapping) proposes to solve this problem by combining the estimation of the vehicle state (localisation : position and orientation) and an incremental modelling of the environment using a perception module (feature detection and matching) in images acquired using one camera or more. Such a perception module requires an important computational load that highly affects the latency and the throughput of the system. Our goal is to implement the SLAM functionality on a low power consumption mixed hardware and software architecture (using a co-design approach) based on a Xilinx Zynq FPGA. This device includes logic cells that allows to speed-up the perception tasks to meet the real-time constraint of an ADAS. In this paper, we present the implementation of two hardware components : a FAST (Features from Accelerated Segment Test) features detector and a parametrizable corner refinement module (Non Maxima Suppression - NMS).

Loop transformations for interface-based hierarchies IN SDF graphs

Data-flow has proven to be an attractive computation model for programming digital signal processing (DSP) applications. A restricted version of data-flow, termed synchronous data-flow (SDF), offers strong compile-time predictability properties, but has limited expressive power. A new type of hierarchy (Interface-based SDF) has been proposed allowing more expressivity while maintaining its predictability. One of the main problems with this hierarchical SDF model is the lack of trade-off between parallelism and network clustering. This paper presents a systematic method for applying an important class of loop transformation techniques in the context of interface-based SDF semantics. The resulting approach provides novel capabilities for integrating parallelism extraction properties of the targeted loop transformations with the useful modeling, analysis, and code reuse properties provided by SDF.

Dataflow Model of Computation

To study the LTE physical layer on multi-core architectures, a Model of Computation (MoC) is needed to specify the LTE algorithms. This MoC must have the necessary expressivity, must show the algorithm parallelism and must be capable of locating system bottlenecks.

Rapid Prototyping and Programming Multi-Core Architectures

This chapter gives an over view of the existing work on rapid prototyping and multi-core deployment in the signal processing world. The concept of rapid prototyping was introduced in Fig. 1.2 when outlining the structure of this document. It consists of automatically generating a system simulation or a system prototype from quickly constructed models. Rapid prototyping may be used for several purposes; this study uses it to manage the parallelism of DSP architectures. Parallelism must be handled differently for the macroscopic or microscopic views of a system.

Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation

This paper proposes an automatic design flow from user-friendly design to efficient implementation of video processing systems. This design flow starts with the use of coarse-grain dataflow representations based on the CAL language, which is a complete language for dataflow programming of embedded systems. Our approach integrates previously developed techniques for detecting synchronous dataflow (SDF) regions within larger CAL networks, and exploiting the static structure of such regions using analysis tools in The Dataflow interchange format Package (TDP). Using a new XML format that we have developed to exchange dataflow information between different dataflow tools, we explore systematic implementation of signal processing systems using CAL, SDF-like region detection, TDP-based static scheduling, and CAL-to-C (CAL2C) translation. Our approach, which is a novel integration of three complementary dataflow tools — the CAL parser, TDP, and CAL2C — is demonstrated on an MPEG Reconfigurable Video Coding (RVC) decoder.

Dataflow LTE Models

The objectives of rapid prototyping are introduced in Chap.1. Figure 6.1 illustrates the process of rapid prototyping. Technical background on the subject is explored in Chapter 4. In this chapter, models for the LTE rapid prototyping process are explained. From these models, execution can be simulated and optimized using multi-core scheduling heuristics and code can also be generated. The LTE models are novel and can complement the standard documents for a better understanding of the LTE eNodeB physical layer. After a general view of the LTE model is given in Sect. 7.2, the three parts of the LTE eNodeB physical layer are detailed in Sects. 7.3–7.5. LTE rapid prototyping is processed by a Java-base framework which includes PREESM. The elements of this framework are introduced in following sections.

Generating Code from LTE Models

Literature on automatic multi-core code generation was reviewed in Sect. 4.5 and scheduling strategies in Sect. 4.4.1. In this section, generated code execution schemes are defined, detailing how code is generated from a given scheduling strategy.