Jonathon E. Colburn

Achieving extreme scan compression for SoC Designs

High volume testing of complex System on Chip (SoC) designs at reasonable test cost requires high test data and test time compression. We present a multilevel scan compression architecture that combines a flexible test compression core with an efficient dynamic broadcast structure and a high speed data access technique. Full X-tolerance, power-aware scan shift and diagnosis are supported through the entire architecture. We present a flow for assembling the various components that limits the impact on area and timing by minimizing test signals and improving modularity of the inserted design-for-test (DFT) structures. These techniques provided a reduction of 600x in test data volume and over 2300x in test time on large Graphics Processor Units (GPU) designs.

Two-level compression through selective reseeding

As scan compression becomes ubiquitous, ever more complex designs require higher compression. This paper presents a novel, two-level compression system for scan input data generated by deterministic test generation. First, load care bits and X-control input data are encoded into PRPG seeds; next, seeds are selectively shared for further compression. The latter exploits the hierarchical nature of large designs with tens or hundreds of PRPGs. The system comprises a new architecture, which includes a simple instruction-decode unit, and new algorithms embedded into ATPG. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage and performance.

Hybrid selector for high-X scan compression

Scan testing and scan compression are widely used, but ever more complex designs require higher compression, while the increased density of unknown (X) values reduces effective compression. In this paper, we present a new selector design which blocks all Xs while allowing more observability of non-X scan cells and which requires fewer input control values. Supported by novel test generation algorithms, the selector enables very high compression even if the density of unknown values is very high and varies every shift. Results on industrial designs with various X densities demonstrate consistently high compression and test coverage.

Test-cost optimization in a scan-compression architecture using support-vector regression

Scan compression is widely used in high-volume testing of complex integrated circuits. With an increase in design complexity, the increased density of unknown (X) values from output responses reduces compression efficiency. In order to effectively block X values and maximize the effectiveness of test compression, a scan-compression architecture has recently been proposed, in which deterministic test patterns can be loaded into selected scan cells by controlling the initial state of the pseudo-random pattern generator (PRPG). A careful selection of the PRPG length is however essential to reduce test cost. We propose an optimization method based on support-vector regression to determine the PRPG length for test-cost reduction in a given scan-compression architecture. A correlation-based feature selection methodology is also proposed to reduce the amount of data needed for the accurate selection of the PRPG length. Experimental results on industrial designs highlight the effectiveness of the proposed method.

Flexible scan interface architecture for complex SoCs

Non-standardized scan interface within and across system-on-chips (SoCs) limits test-data reuse for intellectual properties (IPs). To overcome this limitation, we present a flexible and dynamic scan interface architecture that enables reuse of test-data for a given IP across SoCs with different scan pin configurations. The dynamic nature of this architecture also enables variable shift frequencies across different IPs in a given SoC. The architecture decouples the scan pin requirements from the design cycle of the IPs. It also uses bidirectional scan pins to further reduce test cost by using as few as two pins.

Enhancing testability by structured partial scan

Full scan designs are widely used for their indisputable benefits of predictably high test coverage, diagnosis and debug. However, for high-performance designs the cost of scan - area and delay - is not acceptable and partial scan is used instead. Unfortunately, partial scan significantly increases test generation complexity. We define a structured partial scan design methodology and specific test generation enhancements, which significantly enhance test coverage and reduce test data and cycles. Selective design areas use special types of nonscan cells which can capture a value in the last few scan load cycles. Combinational test generation is extended to work with this structured partial scan design, resulting in higher coverage and fewer patterns. Experimental results on industrial designs show consistent testability benefits.

Dynamic docking architecture for concurrent testing and peak power reduction

Interdependence of the clocking architecture across IPs and overall peak power consumption is a major bottleneck that prevents concurrent yet independent testing of an IP at a higher clock frequency. We use a dynamic clocking architecture that eliminates these dependencies and reduces peak shift power by using clock phase staggering at a granular level during system-on-chip (SoC) testing. A SoC design is typically composed of several Intellectual Property (IPs), some of which may be replicated. Generating a full set of test patterns targeting all IPs at the same time is computationally intensive and may be constrained by project schedule. Using this architecture, production test patterns are generated independently at the IP level and applied concurrently at the SoC level without exceeding the power budget of the chip during test. We present various aspects of the clocking architecture design along with simulation and silicon results to highlight the effectiveness of this architecture.

Innovative practices session 10C: Delay test

The importance of testing for timing related defects continues to increase as devices are manufactured at ever smaller geometries and IO frequencies have increased to the point that production testers can no longer provide stored response vectors at-speed. As a result, it is increasingly important to have high quality tests for delay defects to bring down the products DPPM levels (defective parts per million) shipped to end customers. Moreover, during the design characterization phase, these same tests are also used for isolating systematic slow paths in the design (speedpaths). With the inexorable march toward lower power SKUs, there remains a critical need to find and fix these limiting speedpaths prior to revenue shipments. Over the years, testing for delay defect has morphed from pure functional vectors that try to exercise a device like it would be in an end-user system, to intermediate methods that load assembly code into on-chip caches and execute them at speed, to completely structural methods that utilize scan DFT and check delays at the signal and gate level without resorting to any functional methods at all. This innovative practices session includes three presentations that cover a wide range of topics related to delay testing. The first presentation from Cadence outlines an approach to at-speed coverage that utilizes synergies between clock generation logic, DFT logic and ATPG tools. The solution leverages On-Product Clock Generation logic (OPCG) for high-speed testing and is compatible with existing test compression DFT. The additional DFT proposed enables simultaneous test of multiple clock domains and the inter-domain interfaces, while accounting for timing constraints between them. The ATPG clocking sequences are automatically generated by analyzing the clock domains and interfaces, and this information is used to optimize the DFT structures and for use in the ATPG process. The second presentation discusses the transformation in Intels microprocessor speedpath characterization world over the last few generations, going from pure functional content to scan based structural content. It presents a new “trend based approach” for efficient speedpath isolation, and also delves into a comparison of the effectiveness and correlation of functional vs. structural test patterns for speedpath debug. The third presentation presents the differences between the various delay defect models, namely transition delay, path delay and small-delay, and the pros and cons of each. It goes on to describe new small delay defect ATPG flows implemented at Nvidia that are designed to balance the test generation simplicity of transition delay test patterns and the defect coverage provided by path delay test patterns. These flows enable the small delay defect test patterns to meet the test quality, delivery schedules and ATPG efficiency requirements set by a products test cost goals.