Jong-Arm Jun

Medical Asset Tracking Application with Wireless Sensor Networks

Small sized devices with communication capability are accepted in real applications recent years and the applications increase business efficiency. We developed an asset tracking application using a wireless sensor network. The application consists of three components: a wireless sensor network, a middleware, and a user interface. The sensor network consists of 21 mobile nodes, 29 reference nodes, and one gateway. Each mobile node equipped with a location sensor is attached to one medical asset so that the application tracks 21 medical assets. The middleware abstracts the specification of the sensor network. The graphical user interface is developed according to the requirements of nurses and doctors of Gil Medical Center in Korea so the application fits the asset tracking business of the medical center. The application tracks mobile medical assets in the emergency room of Gil Medical Center. The application shortens the searching time for mobile medical assets from about twenty minutes to within one minute. By shortening the searching time of the assets, the nurses can use more times to take care of patients and the patients can receive better medical services.

Design and implementation of a high-speed ATM host interface controller

The performance increase in computers and ATM networks together with emerging high bandwidth services has resulted in bottleneck at the host-network interfaces. This paper describes the design and implementation of an ATM host interface controller ASIC which relieves the host CPU from processing burdens by doing most of the SAR processing by hardware and also provides high performance. This NIC uses local memory to store control data as well as the received cells and it internally has STMI framer with clock recovery function. The ASIC is a single-chip solution for the implementation of high performance low-cost ATM network adapters for computers having PCI bus.

Enhanced MAC for the bounded access delay

To provide a more reliable link and deterministic delay for the mission-critical services, enhancement of the IEEE 802.15.4-2006 MAC specification was started in March 2008. The enhanced MAC specification offers three types of medium access control: Low Latency (LL), Time Slotted Channel Hopping (TSCH), and Distributed Synchronous Multi-Channel Extension (DSME). In this paper, the link access delay of the LL and DSME MAC is analyzed.

Design and implementation of an ATM segmentation engine with PCI interface

This paper describes the design and implementation of an ATM segmentation engine including PCI interface. This engine, which was designed for an ASIC called ASAH-NIC, contains DMA read machine and segmentation machine. It uses local memory where control information is stored in schedule table, VC table, buffer descriptor and status queue. It has several special features like processing split packet buffers and automatic alignment and packing of transmit data.

Supporting Dynamic Application Programming Environment In Distributed Sensor Networks

Emerging of distributed sensor networks has brought about the need for development of related applications and management environment. This paper suggests a way of designing application reprogrammability capability and management environment for accessing sensor networks.

High-speed IP forwarding mechanism for an MPOA-based switched router

The explosive growth of the Internet traffic has accelerated the proliferation of high speed routers. As todays routers have performance and management limitations, customers are looking for the next generation LAN architectures based on such a high speed technology as ATM. In this paper we present an IP forwarding mechanism for the MPOA-based switched router system, called SR-10, providing MPOA (multiprotocol over ATM) functionality with 10 Gbps ATM switching capability. The SR-10 system can support three kinds of line interfaces: Ethernet, frame relay, and ATM. With a distributed IP processing mechanism, it can provide superior layer-3 transport capability through ATM networks, alleviating bottlenecks and congestion associated with routers and routed paths in the network.

Design of an ASIC for the ATM layer functions

This paper describes the implementation of an ASIC, called ASAH-L (ATM subscriber access handler-logical), for the ATM-layer functions to develop network equipment in B-ISDN. ASAH-L is applicable to network-network interfaces or user-network interfaces and has F4 or F5 level OAM functions with real time processing defined by ITU-TS. Also it provides QOS and network parameter processing, a feature of the OAM. The interface between the ASAH-L and the physical layer functions is the UTOPIA level-1 interface defined by ATM Forum. ASAH-L has two interfaces, 53-octet and 56-octet architecture, for the AAL or ATM switch fabric functions. We have designed all the functions using VHDL. This ASIC, based on gate-arrays, uses 240,000 gates and is packaged in a 240-pin QFP (quad flat package). It is fabricated with 0.6 micron CMOS technology.

An ATM OAM processor for B-ISDN network equipments

The ATM equipment is being introduced very rapidly into private local area networks. The public backbone ATM access network will be established in the near future. It is a very urgent requirement for ATM network equipment to detect a network failure or the service degradation as the ATM service traffic is increased through the public ATM network. It is very important for ATM network equipment to have satisfactory OAM (Operation And Maintenance) solutions. In this paper, we describe the ATM technical requirements which are necessary to support ATM OAM functionalities, represent the functions and architecture of an ATM OAM processor ASIC (ASAH-L), and the top-down ASIC design methodology which we have used.