Jong-Chan Kim

Technology convergence: What developmental stage are we in?

Abstract Despite the enthusiasm for technology convergence seen over the last decade in society and the broad consensus on its considerable impact, there is neither any substantive evidence that technology convergence occurs overall nor any objective explanation of the domains where it may be found. By using patents filed to the KIPO from 1996 to 2010 and demonstrating trends based on co-classification analysis at the entire technology domain level, we elucidate the extent of technology convergence in a technological innovation system and its change in status over time. Furthermore, our paper uses network analysis based on patent data to identify the occurrence of technology convergence in terms of its technological domains. Our findings are as follows: (1) the diffusion of technology convergence has been ongoing since the early 2000s; (2) technology convergence is evolving into a more complex and heterogeneous form; (3) convergent technology has a wider scope but requires more effort to develop than does non-convergent technology; and (4) evidence for the strong consistency of converged domains over time exists. These results support the numerous initiatives of governments and firms to promote technology convergence and illustrate the future form of technology convergence.

Real-Time Program Execution on NAND Flash Memory for Portable Media Players

NAND flash memory has been widely used as a non-volatile storage for storing data. However, it requires a large amount of SRAM for executing program codes stored in it since it only supports page-based reads, not byte-level random reads. This paper proposes a new paging mechanism called RT-PLRU (real-time constrained combination of pinning and LRU) that allows program codes stored in NAND flash memory to be executed satisfying real-time requirements with minimal usage of SRAM. Moreover, the RT-PLRU is optimally configured in a developer-transparent way without giving any burden to the program developer. The developed technique is specifically applied to a media player program targeting a PMP (portable medial player). To the best of our knowledge, this is the first effort to use NAND flash memory as a code storage for storing and executing real-time programs with minimal usage of SRAM.

RT-PLRU: A New Paging Scheme for Real--Time Execution of Program Codes on NAND Flash Memory for Portable Media Players

NAND flash memory has been widely used as a nonvolatile storage for storing data. However, it is challenging to execute program codes on NAND flash memory, since NAND flash memory only supports page-based reads, not byte-level random reads. This paper proposes an automated process to find the optimal paging strategy called RT-PLRU (Real-Time constrained combination of Pinning and LRU) that allows program codes stored in NAND flash memory to be executed satisfying real-time requirements with minimal usage of RAM. Moreover, the proposed process optimally configure the RT-PLRU in a developer-transparent way without giving any burden to the program developer. The developed technique is specifically applied to a media player program targeting a portable media player (PMP). To the best of our knowledge, this is the first effort to use NAND flash memory as a code storage for storing and executing real-time programs with minimal usage of RAM.

Control-Scheduling Codesign Exploiting Trade-Off between Task Periods and Deadlines

A control task’s performance heavily depends on its sampling frequency and sensing-to-actuation delay. More frequent sampling, that is, shorter period, improves the control performance. Similarly, shorter delay also has a positive effect. Moreover, schedulability is also a function of periods and deadlines. By taking into account the control performance and schedulability at the same time, this paper defines a period and deadline selection problem for fixed-priority systems. Our problem is to find the optimal periods and deadlines for given tasks that maximize the overall system performance. As our solution, this paper presents a novel heuristic algorithm that finds a high-quality suboptimal solution with very low complexity, which makes the algorithm practically applicable to large size task sets.

A novel simulation framework for supporting real-time cyber-physical interactions

Simulation methods are widely used when designing complex systems to reduce the development effort and cost. Especially when designing cyber-physical systems (CPSs), the importance of the simulation grows bigger and bigger. To simulate CPSs precisely, a holistic simulator is needed considering cyber and physical systems as a whole. In this paper, we clarify the limitations of the existing simulation techniques and tools when used as CPS simulators: (1) unable to reflect the realtime behavior of the system, (2) do not support interactions with external environments. To overcome these limitations, we specifically propose a two-level simulation architecture and an artificial delay concept. Then, we also address the issues to be considered when the simulator is running on a multi-core system. To apply our proposed technique with concrete application scenarios, we introduce our simulation framework targeting an automotive system simulator.

An efficient and easilly reconfigurable cyber-physical simulator

We propose a new real-time simulation framework for cyber-physical systems (CPSs). It can efficiently dispatch simulation events for real-time simulation of complex events. It can also be easily reconfigured to adapt to various development steps.

mRT-PLRU: A General Framework for Real-Time Multitask Executions on NAND Flash Memory

This paper proposes a novel technique called mRT-PLRU (Multitasking Real-Time constrained combination of Pinning and LRU), which forms a generic framework to use inexpensive nonvolatile NAND flash memory for storing and executing real-time programs in multitasking environments. In order to execute multiple real-time tasks stored in NAND flash memory with the minimal usage of expensive RAM, the mRT-PLRU is optimally configured in two steps. In the first step, the per-task analysis finds the function of RAM size versus execution time (and the corresponding optimal pinning/LRU combination) for each individual task. Using these functions for all the tasks as inputs, the second-step called a stochastic-analysis-in-loop optimization conducts an iterative convex optimization with the stochastic analysis for the probabilistic schedulability check. As a result, the optimization loop can optimally determine the RAM sizes for multiple tasks such that their deadlines are probabilistically guaranteed with the minimal size of total RAM. The usefulness of the developed technique is intensively verified through both simulation and actual implementation. Our experimental study shows that mRT-PLRU can save up to 80 percent of RAM required by the industry-common shadowing approach.

HW Resource Componentizing for Addressing the Mega-complexity of Cyber-physical Systems

Emerging cyber-physical systems (CPSs) demand a new computing abstraction since the traditional ones have fundamental limitations in handling the para-functional also called physical requirements of CPSs such as timeliness, reliability, and evolvability. With the traditional computing abstractions such as processes, virtual memory, etc., multiple software (SW) components share hardware (HW) resources such as CPU and memory in a competitive manner causing unpredictable interferences in the para-functional properties. This problem becomes more serious along with the ever increasing scale and complexity of newly emerging cyber-physical systems. To fundamentally solve this problem, this paper proposes a HW resource componentizing approach that chops the capacity of a HW resource into smaller ones called HW components and dedicates a HW component to each SW component. With the dedicated HW component, each SW component can be guaranteed with the isolated para-functional properties regardless of surrounding SW components. This makes the system-wide issue of validating timeliness, reliability, and evolvability into the per-component validation issue. With this vision, this paper briefly presents a spatial/temporal-division scheduling algorithm that can be generally used for componentizing various HW resources including CPU, network, and RAM.

ECU-in-the-Loop Real-Time Simulation Technique for Developing Integrated Vehicle Safety System

Integrated vehicle safety system is a key issue when developing intelligent safety vehicles. In order to validate such complex systems before actual ECU implementation, ECU-in-the-Loop Simulation (EiLS) is widely used. However, current EiLS methods only simulate the functional behavior of the target system thus cannot validate the temporal behavior of the resulting system. Hence, this paper incorporates a real-time simulation technique such that the target systems both functional and temporal correctness can be validated in the early development phase. For the demonstration purpose, we specifically show how our real-time simulation technique aids the development of the integrated vehicle safety system.

Demo abstract: An efficient and easilly reconfigurable cyber-physical simulator

We propose a new real-time simulation framework for cyber-physical systems (CPSs). It can efficiently dispatch simulation events for real-time simulation of complex events. It can also be easily reconfigured to adapt to various development steps.