Jong-Oh Lee

A Study of Implanted BF2 as a Function of Wafer Temperature During Implant

The temperature effect for buried channel PMOS transistor characteristics was investigated. Generally, only dose, energy and implant angle have been considered as the major parameters for process matching between different high current implanters in transistor manufacturing. However, as the device is scaled down to sub‐100 nm size, additional parameters such as instantaneous dose rate and wafer temperature have become increasingly important for controlling the dopant profile by changing the annealing behavior of defects. The dose rate difference between ribbon and spot beam implanter was investigated through simulation and the wafer temperature difference was directly measured with special temperature measurement device. The peak height of both the boron and fluorine SIMS profiles corresponding to the location of the amorphous/crystalline (a/c) interface increased proportionally with increasing wafer temperature and to a lesser degree with increasing instantaneous dose rate. By increasing the wafer temper...

Investigation of wafer temperature effect during implant for PMOS transistor fabrication

The temperature effect for buried channel PMOS transistor characteristics was investigated. Generally, only dose, energy and implant angle have been considered as the major parameters for process matching between different high current implanters in transistor manufacturing. However, as the device is scaled down to sub-100 nm size, additional parameters such as instantaneous dose rate and wafer temperature have become increasingly important for controlling the dopant profile by changing the annealing behavior of defects. By changing the wafer temperature, the threshold voltage (VT) changed dramatically while the active area sheet resistance remained constant. The peak height of both the boron and fluorine profiles corresponding to the location of the amorphous/crystalline (a/c) interface increased proportionally with increasing wafer temperature and to a lesser degree with increasing instantaneous dose rate. This higher secondary peak height resulted in reduced lateral diffusion, shorter effective channel length, and therefore a lower threshold voltage (VT).

Issues of Ultrashallow Junction for Sub-50 nm Gate Length Transistors: Metrology, Dopant Loss, and Novel Electrostatic Junction

Issues of ultrashallow junctions (USJ) for sub-50 nm gate-length transistors are discussed. To measure the actual current drivability of source/drain extension (SDE), we developed SDE sheet resistance test structure (SSTS) which simulates the actual geometry and thermal condition of dopant underneath sidewall spacer. By using low energy electron induced X-ray emission spectrometry (LEXES) and other conventional techniques such as four point probe (FPP) and secondary ion mass spectrometry (SIMS), we quantified SDE dopant loss during the CMOS process and found that the wet-etching removal and outdiffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively. Novel junction structures with electrostatic channel extension (ESCE) MOSFET for sub-20 nm gate-length transistor are presented as well