Jong-pal Kim

18.3: Implementation of a New Wide Viewing Angle Mode for TFT-LCDs

Compare to the conventional twisted nematic (TN) mode TFT-LCD fabrication process, so far suggested method for the wide viewing angle modes require extra mask-counts. Patterning of the color filter common electrode to achieve the multi-domain vertical alignment (VA) mode costs additional process step. In addition, to avoid improper disclinations, strict alignment margin is necessary. Enhanced vertical alignment (EVA) mode has been developed where the multi-domain cell is formed by the interaction between fringe fields of the pixel electrodes and protrusions on the TFT-array panel. Compared to the TN-mode, since the common electrode is not patterned, EVA mode does not require any additional mask-count. Using the combinations of multi-layer overlap patterns with gate metal, gate dielectrics, passivation nitride, and source/drain metal, protrusions can be formed during the normal TFT-array fabrication process. Viewing angle of the EVA mode can even surpass other wide viewing modes.

Ambient light cancellation in photoplethysmogram application using alternating sampling and charge redistribution technique.

To overcome a large DC offset, ambient light interference, and optical path variation, a robust PPG readout chip is fabricated using 0.13-μm CMOS process. Against the large DC offset, a saturation detection and current feedback method can compensate a current of up to 30 μA. To be robust against optical path variation, an automatic emitting light compensation method is adopted. To remove the ambient light interference, we propose an alternating sampling and charge redistribution technique, in which no additional power is consumed, and only three differential switches and one capacitor are required. The PPG readout channel consumes 26 μW and has a input referred current noise of 260 pArms.

Simple alignment technique for molding and transfer of 3D PDMS structure using the mechanical alignment jig

Simple alignment technique for the purpose of PDMS molding and transfer is proposed. In order to realize suggested technique, specially designed mechanical jig is devised. This jig helps the mechanical alignment and the clamping of the same-sized wafers. Silicon-on-glass wafer is used as a carrier substrate of the thin PDMS structure. 3D PDMS structure for the cap of sensor has been molded and transferred to the sensor using the jig. Though principle and procedure of alignment is very simple, relatively high alignment precision of 10µm has been achieved. All caps of the sensor chips have survived without peeling during dicing process.

Wafer level packaged cantilever array type contact force sensor

The wafer level packaged contact force sensor is presented for applications that require fine pitch measurement. The suggested cantilever array type sensor has high spatial resolution of 210µm. To achieve reliable package, the sensor is capped by PDMS soft cap using wafer level molding and bonding process with 10µm alignment precision. The resistance change over contact force was measured to verify the performance. The good linearity of the result confirms that the PDMS package transfers the forces appropriately. The measured sensitivity is about 4.5%/N.

A 1.2V 83dB DR single-ended input SC ΔΣ modulator including a large-swing analog buffer for portable ECG applications

This study proposes a subsystem consisting of an analog buffer and a single-ended input to a fully differential ΔΣ modulator to obtain low-power consumption for portable electrocardiogram applications. With the proposed subsystem, the need for an inverting amplifier is avoided, and low-power consumption is achieved. The ΔΣ modulator with a second order, 1bit, and cascade of integrators feedforward structure consumes a low power, in which an inverting and a non-inverting path implement a single-ended input to fully-differential signals. A double sampling technique is proposed for a digital-to-analog converter feedback circuit to reduce the effect of the reference voltage, reduce the amplifier requirements, and obtain low-power consumption. Input-bias and output-bias transistors working in the weak-inversion region are implemented to obtain an extremely large swing for the analog buffer. At a supply voltage of 1.2V, signal bandwidth of 250Hz, and sampling frequency of 128kHz, the measurement results show that the modulator with a buffer achieves a 77dB peak signal-to-noise-distortion ratio, an effective-number-of-bits of 12.5 bits, an 83dB dynamic range, and a figure-of-merit of 156dB. The total chip size is approximately 0.28mm2 with a standard 0.13µm Complementary Metal-Oxide-Silicon CMOS process. Copyright

A 1.2 V Low-Power CMOS Chopper-Stabilized Analog Front-End IC for Glucose Monitoring

A low-power 1.2 V CMOS chopper-stabilized analog front-end integrated circuit (IC) for glucose monitoring is presented in this letter. The operating parameters of the IC, including reference voltage in potentiostat, current offset, output gain, and offset, are fully programmable. The IC is fabricated using 0.13-μm CMOS technology, has an active area of 1.4 mm × 4.3 mm, and its power consumption is 30.2 μW. Furthermore, a chopper-stabilized open-loop transimpedance amplifier is proposed for low-power and low-noise implementation. The integrated input-referred current noise is 260 pArms with a bandwidth of 100 Hz.