Jongjib Kim

Optimization of safe-operating-area using two peaks of body-current in submicron LDMOS transistors

The analysis of hot-electron-limited SOA (Safe-Operating-Area) and electrical SOA using two peaks of body current in 20 V LDMOS transistors was investigated for the first time. The origin of the two peaks can be explained in terms of hot carrier injection phenomena. The first peak shows the appearance of weak impact ionization related to the device degradation and the second peak shows the occurrence of the snap-back phenomenon predicting device destruction, respectively.

A high performance complementary bipolar process using PBSOI technique

In this paper, for the first time, we suggest a novel high voltage, high speed and latch-up free NPN transistor and PNP transistor fabrication technology using PBSOI (Patterned and Bonded Silicon On Insulator) and STI (Shallow Trench Isolation) technology. Using this technique, we can easily control the breakdown voltage (BVceo) without the problem of P+B/L out-diffusion. In this PBSOI process, after diffusion of well (collector), the Buried Layer is diffused on the well. In addition, unlike the prior technology that devices are fabricated in epitaxial layer, the proposed devices are formed in active wafer itself, therefore we can get defect-free devices promising excellent characteristics. The peak fTs for NPN and PNP transistor are 10 GHz and 9 GHz, the values of BVceo for the NPN and PNP devices are 15 V and 17 V, respectively. Finally, these values were found to be excellent results as shown in the maximum value of Johnson-limit for the fT-BVceo product.

1200V Interconnection Technique with Isolated Self-Shielding Structure

1200V interconnection technique with the isolated self-shielding concept was verified by simulation and realized without big process changes from the 600V HVIC process conditions. P-substrate resistivity, p-isolation dose, and interlayer thickness, which relieve the electric field under HV interconnection metal line, are found to be the main factors determining breakdown voltage. Experimental results have shown that over 1200V of breakdown voltage without isolation leakage current can be obtained when the p-substrate resistivity of 200ohm.cm and the p-isolation dose of 8.0e12cm-2 are used

Novel lateral 700V DMOS for integration: Ultra-low 85 mΩ ·cm 2 on-resistance, 750V LFCC

A new device concept which is able to break through the silicon limit has been introduced. LFCC (Lateral Floating-Capacitor-Coupled) structure with lateral trench array along drift layer makes drift dose higher than normal RESURF structure with high breakdown voltage. Three dimensional capacitive coupling helps electric field over drift region obtain trapezoidal shape which results in high breakdown voltage with relatively short drift length. Experimental results showed 85 mΩ·cm2 of specific Ron with 750V of breakdown voltage.

A high performance complementary bipolar process controlling base poly-Si over-etching in emitter region and using SOI or PBSOI technique

In this paper, for the first time, we suggest a unique complementary bipolar process which is using the 1st base poly-Si in collector interface, and controlling base poly-Si over-etching in emitter region to obtain high voltage and high speed in NPN tr. and PNP tr. concurrently. And we could find out that the peak fr has a lot of variation according to the degree of base poly silicon over etching. We provide a novel high voltage, high speed and latch-up free complementary process fabrication technology using SOI or PBSOI [J.H. Kim], STI (shallow trench isolation) and DTI (deep trench isolation) technology. The biggest strong point is the NPN and PNP transistors have the same values in terms of size and speed. And also, we have solved the crystal defect generated in SOI substrate. The peak fr for NPN and PNP transistors attained 8.0GHz and 8.5GHz, the BVceo for the NPN and PNP devices achieved 15V and 17V, respectively. These values were found to be excellent results as shown in the maximum value of Johnson-limit for the fT-BVceo product in silicon. [Kwok K.Ng] Currently an operational amplifier product, which is higher than competitors in terms of B/W (band width) at same condition, is being developed with this process.

JFET pinched bootstrap diode (JPBD) without substrate leakage current integration to 120V BCDMOS process

A new concept to realize the usage of a high-voltage bootstrap diode without substrate leakage current for 120 V high-side-driver application is proposed and verified by 2D simulation. The combination of high-voltage (HV) JFET and medium-voltage (MV) diode with proper modification to avoid substrate leakage current at forward conduction state and high-blocking voltage at off state for integrated bootstrap operation is proposed. Simulation results showed 130 V of breakdown voltage and 0.79 V of FVD (forward voltage drop) @ 100 A/cm2 without substrate leakage current at conduction mode.