Jongsu Park

A low-power Booth multiplier using novel data partition method

The Booth algorithm has a characteristic that the Booth algorithm produces the Booth encoded products with a value of zero when input data stream have sequentially equal values. Therefore, partial products have greater chances of being zero when the one with a smaller dynamic range of two inputs is used as a multiplier. To minimize greater switching activities of partial products, we propose a novel multiplication algorithm and its associated architecture. The proposed algorithm divides a multiplication expression into four multiplication expressions, and each multiplication is computed independently. Finally, the results of each multiplication are added. Therefore, the exchanging rate of two input data calculations can be higher during multiplication. Implementation results show the proposed multiplier can maximally save about 20% in terms of power dissipation than the previous Booth multiplier.

Embedded network camera processor system on a chip for various low-power multimedia applications

In this paper we present an embedded network camera processor (NCP) system on a chip (SoC) for various low-power multimedia applications. The NCP SoC comprises a digital camera processor optimized for a CCD sensor, a motion JPEG encoder to compress the data, an Ethernet controller to transmit the data, ARM processor and many peripherals. Using the NCP SoC allows the raw image from a CCD sensor to be filtered, compressed and transmitted anywhere through various Ethernet protocols, with no additional hardware. The NCP SoC is designed with Verilog-HDL. Also, we followed a strict ASIC flow including functional behavior verification and a scan test. The NCP SoC is fabricated with 0.25

System Level Design of Reconfigurable Server Farms Using Elliptic Curve Cryptography Processor Engines

{\upmu }{\text {m}}

Network security camera system and its application for consumer electronics in ubiquitous environment

μm CMOS technology. The total chip size, including embedded memory, is

Circuit Switching-Based Pipelined Broadcast Algorithm and Its Architecture to Improve Message Passing Interface Communications on Multiprocessor System-on-Chip

7800\times 7800\,{\upmu }{\text {m}}^{2}

Robust Frequency Offset Estimation Using Relationships Among Adjacent Packets for Inter-Vehicle Communication Systems

7800×7800μm2 and the gate count is 1.2 million. The NCP SoC runs at up to 48 MHz, and supports various slower clock frequencies for low-power applications requiring additional power saving modes: 6 MHs, 12 and 24 MHz at 2.5 V.