Joon-Young Paik

Performance Improvement for Flash Memories Using Loop Optimization

Flash memories have advanced features such as non-volatility, fast access speed, and low power consumption that they are adopted in various ubiquitous portable devices. However, the speed of writing on flash memory is relatively slower than that of reading, and extensive research efforts are devoted to overcome these restrictions, mostly in the field of flash translation layers (FTLs). This paper proposes an orthogonal approach of reducing flash memory writing time, by detecting and eliminating unnecessary write operations before execution of embedded applications. For this purpose, we extend static analysis techniques previously used in the compilers for program optimization. Our research focuses on loop blocks, which are usually used for massive data management and likely to efficiently enhance performance when improved. As a result, we show that the proposed method reduces the amount of data to be written and improves the writing performance for flash memories.

An Integrated Formal Model for Context-Aware Systems

Context-aware applications should consider the devices and networks engaged in the systems, as well as the complex control and data structures in the applications. This makes it not so straightforward to understand applications and to achieve the quality of applications, without well-defined formal model adequate to the intended goals. In this paper, we propose a formal model for context aware system, which provides device behaviors with temporal features, enriched with commonly used categorization of context. Thus this model enables integrated management of the interconnected devices with context information for a context-aware system, so as to be employed for the critical purposes like safety enhancement.

Reorganizing Data Blocks in Flash Memory by Program Translation

Due to the portability, low power consumption and robustness, flash memory is one of the popular storage devices for small electronic equipments like smart phones and PMPs (Portable multimedia players). However, it suffers from performance bottlenecks caused by asymmetric speed between read and write operations. A lot of previous researches focused on improving address mapping schemes in FTL (Flash Translation Layer) to reduce the number of write operations which are more expensive, but they rarely consider semantic factors like data file formats and detailed sequence of write operations. In this paper we suggest a new performance enhancement technique for flash memory, where a file format is reorganized to segregate read-only data and writable data. Since converting every standardized data format to a new one is unrealistic, we use static analysis and program translation--the transformed programs keep the writable data in the same block, rather than allowing it to be scattered over a larger number of blocks mixed with read-only data.

Log-buffer aware cache replacement policy for flash storage devices

In recent years, flash memory has been widely used in embedded devices and enterprise computing environments because of its many advantages, which includes shock resistance, low energy consumption, non-volatile nature and high I/O speed. However, flash memory hardware also possesses characteristics such as erase-before write, a limited number of erase cycles and asymmetric I/O costs among read, write, and erase operations, where the cost of write and erase operations are much higher than that of read operations. Hence, there is the need for the cache-replacement policy in flash-based systems to consider the asymmetric I/O costs. Previous studies on cache management including least recently used (LRU), clean-first LRU (CFLRU) and cold clean-first LRU (CCF-LRU) focused mainly on to reducing the write access to flash memory by evicting clean pages before dirty pages, and they do not consider how the evicted page would be treated by the flash memory. This resulted in performance degradation. Flash aware buffer-management (FAB) tries to evict pages considering the inner structure of flash memory but there are problems related to the high cache-miss ratio and the generation of a large number of write operations to the flash memory. This paper proposes a log-buffer aware (LBA) cache-replacement policy that not only tries to reduce the number of write accesses to flash memory as well as the high cache hit ratio, but also evicts pages while considering the log-block associativity problem of log-based flash translation layers (FTLs). Experimental results show that compare to previous studies, the proposed cache-replacement policy is more effective for higher cache-hit ratio and for reducing the garbage-collection overhead of flash memory by increasing the partial merge and switch operation.

Automated Crash Filtering for ARM Binary Programs

This paper aims to help to differentiate security related crashes from benign vulnerabilities, using static taint-analysis. To achieve this goal, we propose a tool named Crash Filter, which determines if a crash can be made to be exploitable or not, by analyzing ARM binary codes. We envision that the proposed analysis would help to timely fix security-critical bugs.

Cost Model Based Analyses on Performance Effects of Loop Transformations in Block Associative Sector Translation

In this paper, we investigate how traditional loop transformations affect flash memory performance. To do so, we propose cost models of loop structures in BAST (Block Associative Sector Translation) on flash memory. The proposed cost models reflect not only distinctive characteristics of flash memory but also loop structures, making these new models suitable to loop structures compared with previous cost models. Based on these cost models, we analyze the performance effects of loop transformation, and then determined the referenced order and stride variables which influence the performance in BAST. From the cost models and the experiments, we find out that loop distribution and loop fusion rarely affect performance, while that loop reversal and loop interchange apparently do, due to the one log block to one data block property of BAST. In addition, some loop transformations, when applied to flash memory based programs, can cause unexpected performance variations.

Loop transformations for flash memory: cost models and performance effects

Loop optimization, made of a sequence of loop transformations, plays an important role in performance improvement in data centric applications. Programs using flash memory are no exception to this, but, under certain conditions careless applications of specific loop transformations might cause unexpected results, due to the characteristics of flash memory and underlying management systems. In this article, we analyze how loop transformations affect the performance in flash translation layers (FTLs). First, we choose four loop structures which have distinct reference patterns and propose a cost model for each structure, reflecting the properties of flash memory. Then, using these cost models, we investigate how loop transformations affect the block associative sector translation (BAST)’s and fully associative sector translation (FAST)’s internal operations and analyze the performance effect of loop transformations experimentally. As a result, we find that some of the major loop transformations cause unexpected performance effects in those major FTLs under certain conditions.

A Lingustic Approach for Robustness in Context Aware Applications

Context-aware applications are vulnerable to errors due to the devices and networks engaged in the systems, as well as the complex control and data structures in the applications. Although usually fault tolerant technologies and software verifications are widely used to prevent and remedy errors, we notice that programming languages used in developing context-aware applications also play important roles in generating less error-prone programs. In this paper we introduce our recent efforts devoted to devising a programming language supporting safety related features and formal semantics for context aware applications.

Profiling-Based Log Block Replacement Scheme in FTL for Update-Intensive Executions

FTL (Flash Translation Layer) hides details of flash memory, providing file systems with an abstract view of the flash memory. For NAND flash memory, some previous researches have achieved dramatic performance enhancement by adopting log-based FTL, which records time-consuming write operations in log blocks, rather than executes them immediately. Log block replacement scheme plays an essential role in this method, due to the limitation of pre-reserved log block space, this method entails selecting some victims from the existing blocks and re-use them for newly issued operations. However, simple replacement algorithms are vulnerable to select such log blocks that will be used soon, which causes performance degradation. In this paper we propose a smarter log block replacement scheme to alleviate this problem by keeping busy log blocks from being selected, based on profiling and analyzing log block status. We show that our scheme reduces unnecessary time-consuming write operations and achieves performance improvement especially for the applications having intensive locality.

RFTL: improving performance of selective caching-based page-level FTL through replication

The internal nature of flash memory technology, makes its performance highly dependent on workload characteristics causing poor performance on random writes. To solve this, Demand-based Flash Translation Layer (DFTL) which selectively caches page-level address mappings, was proposed. DFTL exploits temporal locality in workloads and when low, high cache miss rates are experienced. In this paper, we propose a replication based DFTL, called RFTL, which aims at minimizing the overhead caused by miss penalty from the cached mapping table in SRAM. We developed an analytical model for studying the range of performance for RFTL. We extended EagleTree simulator to implement RFTL. Our experimental evaluation with synthetic workloads endorses the utility of RFTL showing improved performance over DFTL especially for read-dominant workloads. With 80% read dominant workload, RFTL’s cumulative distribution function shows a 20% improvement and under 80% write dominant workload, it outperforms DFTL by 10% on I/O throughput.