Joonho Lim

A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems

In this paper, we describe an energy-efficient carry-lookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversible adiabatic logic. We also describe an eight-phase, clocked power generator that requires an off-chip inductor. For the energy-efficient design of reversible logic, we explain how to control the overhead of reversibility with a self-energy-recovery circuit. A test chip was implemented with a 0.8 /spl mu/m CMOS technology, which included two 16-bit carry-lookahead adders to allow fair comparison: an RERL one and a static CMOS one. Experimental results showed that the RERL adder had substantial advantages in energy consumption over the static CMOS one at low operating frequencies. We also confirmed that we could minimize the energy consumption in the RERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal.

nMOS reversible energy recovery logic for ultra-low-energy applications

We propose a new fully reversible adiabatic logic, nMOS reversible energy recovery logic (nRERL), which uses nMOS transistors only and a simpler 6-phase clocked power. Its area overhead and energy consumption are smaller, compared with the other fully adiabatic logics. We employed bootstrapped nMOS switches to simplify the nRERL circuits. With the simulation results for a full adder, we confirmed that the nRERL circuit consumed substantially less energy than the other adiabatic logic circuits at low-speed operation. We evaluated a test chip implemented with 0.8-/spl mu/m CMOS technology, which included a chain of nRERL inverters integrated with a clocked power generator. The nRERL inverter chain of 2400 stages consumed the minimum energy at V/sub dd/=3.5 V at 55 kHz, where the adiabatic and leakage losses are about equal, which is only 4.50% of the dissipated energy of its corresponding CMOS circuit at V/sub dd/=0.9 V. In conclusion, nRERL is more suitable than the other adiabatic logic circuits for the applications that do not require high performance but low energy consumption.

An 8×8 nRERL serial multiplier for ultra-low-power aplications

The test chip was fabricated with the help of IDEC program of KAIST, Taejon, Korea. This paper was sup- ported by NON DIRECTED RESEARCH FUND, Korea Research Foundation,throught Inter-university Semicon- ductor Research Center, Seoul National University, Seoul, Korea, from 1996 to 1999.

Digital implementation of discrete-time cellular neural networks with distributed arithmetic

We propose an efficient digital architecture for the discrete-time cellular neural networks (DTCNNs). That is based on the combination of the bit-serial computation of distributed arithmetic (DA) with the characteristics of the DTCNN: the local connectivity and the translation invariance in the templates. Implementation of the DTCNN with the proposed architecture requires a reduced hardware complexity and a small number of bus lines. It consumes less silicon area because of the bit-serial computation of DA and offers higher speed operation than the analog implementations of the DTCNN. A DTCNN cell was implemented in a 0.8 /spl mu/m CMOS technology. The experimental results show that the maximum operation frequency of chip is 30 MHz.

Ratio pulse arithmetic for radial basis function network

Ratio pulse arithmetic represents a signal with a random pulse stream and its value is defined as the ratio of ones and zeroes in its random pulse stream. We propose circuits for the exponential function and subtraction, and explain how to implement a radial basis function (RBF) network. We applied the RBF network to a classifier example. Simulation results show that its performance is comparable to that of a conventional RBF network.

Character recognition by neural networks with single-layer training and rejection mechanism

For many real applications of pattern classification problems, it is more important to reduce the misclassification rate than to increase the rate of successful classification. In this paper, we propose a single-layer neural network with two rejection mechanisms for character recognition problems, which guarantees a very low misclassification rate. The proposed architecture is a cascaded connection of an SLP network and a simple combinational circuit. Comparing to the MLP network, it yields fast learning and requires a simple hardware architecture. We also introduce a new linearly separable coding scheme for training the SLP network to reduce the misclassification rate. We prepared two databases: one with 135,000 digit patterns and the other with 117,000 letter patterns. Then we applied the proposed method to the classification problem for the databases and results show that the misclassification rate is significantly low with maintaining a high recognition rate.<<ETX>>

An 8/spl times/8-b nRERL serial multiplier for ultra-low-power applications

An 8/spl times/8-b nRERL serial multiplier is implemented in a 0.6-/spl mu/m n-well 3-metal CMOS process. nRERL (nMOS Reversible Energy Recovery Logic) is a new reversible adiabatic logic circuit, which can be operated at the leakage-current level for ultra-low-energy applications. Measurement results showed that the nRERL serial multiplier consumed only 0.9% of the energy dissipation by the static CMOS type at the operating frequency 100 kHz at 5 V, where its adiabatic and leakage losses were about equal.