Joonhwan Yi

The coupling model for function and delay faults

We propose a high-level fault model, the coupling fault (CF) model, that aims to cover both functional and timing faults in an integrated way. The basic properties of CFs and the corresponding tests are analyzed, focusing on their relationship with other fault models and their test requirements. A test generation program COTEGE for CFs is presented. Experiments with COTEGE are described which show that (reduced) coupling test sets can efficiently cover standard stuck-at-0/1 faults in a variety of different realizations. The corresponding coupling delay tests detect all robust path delay faults in any realization of a logic function.

Cycle error correction in asynchronous clock modeling for cycle-based simulation

As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficient methodology for system verification because of its fast simulation speed. The cycle-based simulation has a limitation in using asynchronous clocks that causes inherent cycle errors. In order to reuse the output of a C-level cycle-based simulation for the verification of a lower level model, the C-level model should be cycle-accurate with respect to the lower level model. In this paper, a cycle error correction technique is presented for two asynchronous clock models. An example design is devised to show the effectiveness of the proposed method. Our experimental results show that the fast speed of cycle-based simulation can be fully exploited without sacrificing the cycle accuracy

An interpolation method for strong barrel lens distortion

We propose an interpolation method considering strong barrel distortion of a fisheye lens using nearest pixels on a corrected image. The correction of barrel distortion comprises coordinate transformation and interpolation, and this paper focuses on interpolation. The proposed interpolation method uses nearest coordinates on a corrected image rather than on a distorted image, unlike existing techniques. The increased computational complexity of the proposed interpolation method is alleviated by using look-up table (LUT)-based optimization. Experimental results show that both subjective and objective image qualities are improved with marginal execution time.

Modeling and performance analysis for a receiver-initiated MAC protocol in wireless sensor networks

Energy efficiency is a very important requirement in designing a MAC protocol for wireless sensor networks using battery-operated sensor nodes. We proposed a new energy-efficient MAC protocol, RIX-MAC, based on asynchronous duty cycling and receiver-initiated scheme. In this article, we analyze the performance such as throughput, delay, and energy consumption of RIX-MAC with modeling and simulation. For mathematical analysis, we first use the Markov chain model and determine the transmission and state probabilities and set the equations to solve throughput and delay. We also calculate the energy consumption by separating a cycle period into TX and RX durations. Our analysis results are validated by comparing with the simulation results obtained by NS-2.

Robust Coupling Delay Test Sets

One of the most challenging problems in high-level testing is to reduce the size of a high-level test set while ensuring an adequate fault coverage for various implementations of a function under test. A small and high-coverage test set called a robust coupling delay test set (RCDTS) is derived from the coupling delay test set proposed previously. A partial ordering relationship among delay tests in certain implementations called “restricted” gate networks is used to reduce the size of test sets. The RCDTS still detects all robust path delay faults. This result is extended further to the more general balanced inversion parity networks. A test generation program RTGEN for RCDTSs is then developed, and experiments with it show that significant test set reduction can be achieved.

A data flow optimization method for high speed MAC processing in an IEEE 802.16m modem

IEEE 802.16m technology is expected to provide high speed packet data service over wireless. Due to the large amount of data to be processed over a short period of time, an efficient MAC processing in the modem is crucial. Since the MAC processing algorithm has optimization limitations, we focus on a data flow optimization in the system level design, so that the number of external memory accesses is minimized. Experimental results show that our approach results in an up to sixteen times faster IEEE 802.16m modem system.

Industrial experience with cycle error computation of cycle-accurate transaction level models

Transaction level modeling is gaining increasing popularity with the increasing design complexity of the system-on-a-chip. Transaction level models are frequently built from existing register transfer level models, which usually cause cycle errors. Measurable indicators of cycle errors are necessary, and their definitions are important. This paper presents the challenges in cycle error computation and our proposed method, although its effectiveness has not been proved formally. The main contribution of our study is to report an industrial experience with cycle error computation.